97 lines
2.7 KiB
Verilog
97 lines
2.7 KiB
Verilog
/**
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* The HACK computer, including CPU, ROM, RAM and the generator for
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* reset and clk (25MHz) signal. For approx. 20us HACK CPU resets.
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* From this point onward the user is at the mercy of the software.
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* In particular, depending on the program's code, the LED may show
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* some output and the user may be able to interact with the computer
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* via the BUT.
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*/
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`default_nettype none
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module HACK(
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input CLK, // external clock 100 MHz
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input [1:0] BUT, // user button (0 if pressed, 1 if released)
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output [1:0] LED // leds (0 off, 1 on)
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);
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wire loadRAM;
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wire loadIO0;
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wire loadIO1;
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wire loadIO2;
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wire loadIO3;
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wire loadIO4;
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wire loadIO5;
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wire loadIO6;
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wire loadIO7;
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wire loadIO8;
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wire loadIO9;
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wire loadIOA;
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wire loadIOB;
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wire loadIOC;
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wire loadIOD;
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wire loadIOE;
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wire loadIOF;
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wire [15:0] inRAM;
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wire [15:0] inIO0;
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wire [15:0] inIO1;
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wire [15:0] inIO2=0;
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wire [15:0] inIO3=0;
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wire [15:0] inIO4=0;
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wire [15:0] inIO5=0;
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wire [15:0] inIO6=0;
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wire [15:0] inIO7=0;
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wire [15:0] inIO8=0;
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wire [15:0] inIO9=0;
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wire [15:0] inIOA=0;
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wire [15:0] inIOB;
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wire [15:0] inIOC;
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wire [15:0] inIOD;
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wire [15:0] inIOE;
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wire [15:0] inIOF;
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wire writeM;
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wire [15:0] inM;
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wire [15:0] instruction;
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wire [15:0] outM;
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wire [15:0] addressM;
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wire [15:0] pc;
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wire clk, reset;
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wire [15:0] outDEBUG0;
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wire [15:0] outDEBUG1;
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wire [15:0] outDEBUG2;
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wire loadDEBUG0;
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wire loadDEBUG1;
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wire loadDEBUG2;
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// Put your code here:
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assign LED[1:0] = inIO0[1:0];
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assign outDEBUG0 = inIOB;
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assign outDEBUG1 = inIOC;
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assign outDEBUG2 = inIOD;
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assign loadDEBUG0 = loadIOB;
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assign loadDEBUG1 = loadIOC;
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assign loadDEBUG2 = loadIOD;
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Clock25_Reset20 CLKR(CLK, clk, reset);
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CPU CPU(clk, inM, instruction, reset, outM, writeM, addressM, pc);
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Memory Memory(addressM, writeM, inM, loadRAM,
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loadIO0, loadIO1, loadIO2, loadIO3, loadIO4, loadIO5, loadIO6, loadIO7,
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loadIO8, loadIO9, loadIOA, loadIOB, loadIOC, loadIOD, loadIOE, loadIOF,
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inRAM, inIO0, inIO1, inIO2, inIO3, inIO4, inIO5, inIO6, inIO7,
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inIO8, inIO9, inIOA, inIOB, inIOC, inIOD, inIOE, inIOF);
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ROM ROM(pc, instruction);
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RAM3840 RAM(clk, addressM[11:0], outM, loadRAM, inRAM);
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Register LED12(clk, outM, loadIO0, inIO0);
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Register BUT12(clk, {14'b0, BUT[1:0]}, 1'b1, inIO1);
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Register DEBUG0(clk, outM, loadIOB, inIOB);
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Register DEBUG1(clk, outM, loadIOC, inIOC);
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Register DEBUG2(clk, outM, loadIOD, inIOD);
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Register DEBUG3(clk, outM, loadIOE, inIOE);
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Register DEBUG4(clk, outM, loadIOF, inIOF);
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endmodule
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