28 lines
761 B
Verilog
28 lines
761 B
Verilog
/**
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* Uses CLK of 100MHz to generate:
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* internal clock signal clk with 25MHz and
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* a reset signal of approx. 20us length
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*/
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`default_nettype none
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module Clock25_Reset20(
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input CLK, // external clock 100 MHz
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output reg clk, // internal clock 25 Mhz
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output reg reset // reset signal approx. 20us
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);
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// Put your code here:
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reg boot=1;
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reg [3:0] ccount=0;
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reg [12:0] rcount=0;
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always @(posedge CLK) begin
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if (boot == 1) begin
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boot <= (rcount == 4095) ? 0 : 1;
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rcount <= (rcount == 4095) ? 0 : rcount + 1;
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reset <= (rcount >= 2048) ? 0 : 1;
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end
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ccount <= (ccount == 3) ? 0 : ccount + 1;
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clk <= (ccount >= 2) ? 1 : 0;
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end
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endmodule
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