27 lines
580 B
Verilog
27 lines
580 B
Verilog
/**
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* RAM512 implements 512 Bytes of RAM addressed from 0 - 511
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* out = M[address]
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* if (load =i= 1) M[address][t+1] = in[t]
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*/
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`default_nettype none
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module RAM512(
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input clk,
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input [8:0] address,
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input [15:0] in,
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input load,
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output [15:0] out
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);
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// Put your code here:
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wire load0;
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wire load1;
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wire [15:0] ram0;
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wire [15:0] ram1;
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DMux DMUX(load, address[8], load0, load1);
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RAM256 RAM0(clk, address[7:0], in, load0, ram0);
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RAM256 RAM1(clk, address[7:0], in, load1, ram1);
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Mux16 MUX(ram0, ram1, address[8], out);
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endmodule
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