49 lines
1.2 KiB
Verilog
49 lines
1.2 KiB
Verilog
/**
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* RAM3840 implements 3840 Bytes of RAM addressed from 0 - 3839
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* out = M[address]
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* if (load =i= 1) M[address][t+1] = in[t]
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*/
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`default_nettype none
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module RAM3840(
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input clk,
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input [11:0] address,
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input [15:0] in,
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input load,
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output [15:0] out
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);
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// Put your code here:
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wire load0;
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wire load1;
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wire load2;
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wire load3;
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wire load4;
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wire load5;
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wire load6;
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wire load7;
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wire [15:0] ram0;
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wire [15:0] ram1;
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wire [15:0] ram2;
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wire [15:0] ram3;
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wire [15:0] ram4;
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wire [15:0] ram5;
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wire [15:0] ram6;
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wire [15:0] ram7;
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DMux8Way DMUX(load, address[11:9],
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load0, load1, load2, load3, load4, load5, load6, load7);
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RAM512 RAM0(clk, address[8:0], in, load0, ram0);
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RAM512 RAM1(clk, address[8:0], in, load1, ram1);
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RAM512 RAM2(clk, address[8:0], in, load2, ram2);
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RAM512 RAM3(clk, address[8:0], in, load3, ram3);
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RAM512 RAM4(clk, address[8:0], in, load4, ram4);
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RAM512 RAM5(clk, address[8:0], in, load5, ram5);
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RAM512 RAM6(clk, address[8:0], in, load6, ram6);
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RAM256 RAM7(clk, address[7:0], in, load7, ram7);
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Mux8Way16 MUX(ram0, ram1, ram2, ram3, ram4, ram5, ram6, ram7,
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address[11:9], out);
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endmodule
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