63 lines
1.8 KiB
Verilog
63 lines
1.8 KiB
Verilog
/**
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* 8-bit Shiftregister (shifts to left)
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* if (load == 1) out[t+1] = in[t]
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* else if (shift == 1) out[t+1] = out[t]<<1 | inLSB
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* (shift one position to left and insert inLSB as least significant bit)
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*/
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`default_nettype none
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module BitShift8L(
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input clk,
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input [7:0] in,
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input inLSB,
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input load,
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input shift,
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output [7:0] out
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);
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// Put your code here:
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reg [7:0] reg8;
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always @(posedge clk) begin
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if (load == 1) begin
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reg8[7:0] = in[7:0];
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end
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else if (shift == 1 ) begin
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reg8[7:1] = reg8[6:0];
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reg8[0] = inLSB;
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end
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end
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assign out = reg8;
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// wire [7:0] out_l;
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// wire [7:0] out_s;
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// Mux MUXLA(out[0], in[0], load, out_l[0]);
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// Mux MUXLB(out[1], in[1], load, out_l[1]);
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// Mux MUXLC(out[2], in[2], load, out_l[2]);
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// Mux MUXLD(out[3], in[3], load, out_l[3]);
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// Mux MUXLE(out[4], in[4], load, out_l[4]);
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// Mux MUXLF(out[5], in[5], load, out_l[5]);
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// Mux MUXLG(out[6], in[6], load, out_l[6]);
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// Mux MUXLH(out[7], in[7], load, out_l[7]);
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// Mux MUXSA(out_l[0], inLSB, shift, out_s[0]);
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// Mux MUXSB(out_l[1], out[0], shift, out_s[1]);
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// Mux MUXSC(out_l[2], out[1], shift, out_s[2]);
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// Mux MUXSD(out_l[3], out[2], shift, out_s[3]);
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// Mux MUXSE(out_l[4], out[3], shift, out_s[4]);
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// Mux MUXSF(out_l[5], out[4], shift, out_s[5]);
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// Mux MUXSG(out_l[6], out[5], shift, out_s[6]);
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// Mux MUXSH(out_l[7], out[6], shift, out_s[7]);
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// Bit BITA(clk, out_s[0], 1'b1, out[0]);
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// Bit BITB(clk, out_s[1], 1'b1, out[1]);
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// Bit BITC(clk, out_s[2], 1'b1, out[2]);
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// Bit BITD(clk, out_s[3], 1'b1, out[3]);
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// Bit BITE(clk, out_s[4], 1'b1, out[4]);
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// Bit BITF(clk, out_s[5], 1'b1, out[5]);
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// Bit BITG(clk, out_s[6], 1'b1, out[6]);
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// Bit BITH(clk, out_s[7], 1'b1, out[7]);
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endmodule
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