19 lines
316 B
Verilog
19 lines
316 B
Verilog
/**
|
|
* 16-bit incrementer:
|
|
* out = in + 1 (arithmetic addition)
|
|
*/
|
|
|
|
`default_nettype none
|
|
module Inc16(
|
|
input [15:0] in,
|
|
output [15:0] out
|
|
);
|
|
|
|
// Put your code here:
|
|
wire [15:0] incr;
|
|
assign incr[15:0] = 16'b1;
|
|
Add16 ADD(in, incr, out);
|
|
// or just:
|
|
//assign out = in + 1;
|
|
endmodule
|