49 lines
1.4 KiB
Verilog
49 lines
1.4 KiB
Verilog
/**
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* Adds two 16-bit values.
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* The most significant carry bit is ignored.
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* out = a + b (16 bit)
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*/
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`default_nettype none
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module Add16(
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input [15:0] a,
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input [15:0] b,
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output [15:0] out
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);
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// Put your code here:
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wire carry0;
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wire carry1;
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wire carry2;
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wire carry3;
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wire carry4;
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wire carry5;
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wire carry6;
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wire carry7;
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wire carry8;
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wire carry9;
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wire carry10;
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wire carry11;
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wire carry12;
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wire carry13;
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wire carry14;
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wire carry15;
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HalfAdder HA0(a[0], b[0], out[0], carry0);
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FullAdder FA0(a[1], b[1], carry0, out[1], carry1);
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FullAdder FA1(a[2], b[2], carry1, out[2], carry2);
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FullAdder FA2(a[3], b[3], carry2, out[3], carry3);
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FullAdder FA3(a[4], b[4], carry3, out[4], carry4);
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FullAdder FA4(a[5], b[5], carry4, out[5], carry5);
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FullAdder FA5(a[6], b[6], carry5, out[6], carry6);
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FullAdder FA6(a[7], b[7], carry6, out[7], carry7);
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FullAdder FA7(a[8], b[8], carry7, out[8], carry8);
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FullAdder FA8(a[9], b[9], carry8, out[9], carry9);
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FullAdder FA9(a[10], b[10], carry9, out[10], carry10);
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FullAdder FA10(a[11], b[11], carry10, out[11], carry11);
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FullAdder FA11(a[12], b[12], carry11, out[12], carry12);
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FullAdder FA12(a[13], b[13], carry12, out[13], carry13);
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FullAdder FA13(a[14], b[14], carry13, out[14], carry14);
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FullAdder FA14(a[15], b[15], carry14, out[15], carry15);
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endmodule
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