101 lines
3.1 KiB
Verilog
101 lines
3.1 KiB
Verilog
/**
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* The ALU (Arithmetic Logic Unit).
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* Computes one of the following functions:
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* x+y, x-y, y-x, 0, 1, -1, x, y, -x, -y, !x, !y,
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* x+1, y+1, x-1, y-1, x&y, x|y on two 16-bit inputs,
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* according to 6 input bits denoted zx,nx,zy,ny,f,no.
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* In addition, the ALU computes two 1-bit outputs:
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* if the ALU output == 0, zr is set to 1; otherwise zr is set to 0;
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* if the ALU output < 0, ng is set to 1; otherwise ng is set to 0.
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*/
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// Implementation: the ALU logic manipulates the x and y inputs
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// and operates on the resulting values, as follows:
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// if (zx == 1) set x = 0 // 16-bit constant
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// if (nx == 1) set x = !x // bitwise not
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// if (zy == 1) set y = 0 // 16-bit constant
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// if (ny == 1) set y = !y // bitwise not
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// if (f == 1) set out = x + y // integer 2's complement addition
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// if (f == 0) set out = x & y // bitwise and
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// if (no == 1) set out = !out // bitwise not
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// if (out == 0) set zr = 1
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// if (out < 0) set ng = 1
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`default_nettype none
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module ALU(
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input [15:0] x, // input x (16 bit)
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input [15:0] y, // input y (16 bit)
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input zx, // zero the x input?
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input nx, // negate the x input?
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input zy, // zero the y input?
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input ny, // negate the y input?
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input f, // compute out = x + y (if 1) or x & y (if 0)
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input no, // negate the out output?
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output [15:0] out, // 16-bit output
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output zr, // 1 if (out == 0), 0 otherwise
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output ng // 1 if (out < 0), 0 otherwise
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);
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// Put your code here:
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wire [15:0] xa;
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wire [15:0] xb;
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wire [15:0] xc;
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wire [15:0] ya;
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wire [15:0] yb;
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wire [15:0] yc;
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wire [15:0] xandy;
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wire [15:0] xplusy;
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wire [15:0] xf;
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wire [15:0] xn;
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wire [7:0] zri;
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wire [7:0] zrj;
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wire ngr;
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wire zrm;
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wire zrn;
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wire zro;
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wire tt;
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wire ff;
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// Mux16(a=x, b=false, sel=zx, out=xa);
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// Not16(in=xa, out=xb);
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// Mux16(a=xa, b=xb, sel=nx, out=xc);
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Mux16 MUXX1(x, 16'b0, zx, xa);
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Not16 NOTX1(xa, xb);
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Mux16 MUXX2(xa, xb, nx, xc);
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// Mux16(a=y, b=false, sel=zy, out=ya);
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// Not16(in=ya, out=yb);
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// Mux16(a=ya, b=yb, sel=ny, out=yc);
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Mux16 MUXY1(y, 16'b0, zy, ya);
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Not16 NOTY1(ya, yb);
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Mux16 MUXY2(ya, yb, ny, yc);
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// And16(a=xc, b=yc, out=xandy);
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// Add16(a=xc, b=yc, out=xplusy);
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// Mux16(a=xandy, b=xplusy, sel=f, out=xf);
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And16 ANDZ1(xc, yc, xandy);
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Add16 ADDZ1(xc, yc, xplusy);
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Mux16 MUXZ1(xandy, xplusy, f, xf);
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// Not16(in=xf, out=xn);
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// Mux16(a=xf, b=xn, sel=no, out=out, out[15]=ngr, out[0..7]=zri, out[8..15]=zrj);
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Not16 NOTF1(xf, xn);
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Mux16 MUXF1(xf, xn, no, out);
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assign ngr = out[15];
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assign zri[7:0] = out[7:0];
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assign zrj[7:0] = out[15:8];
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// Or8Way(in=zri, out=zrm);
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// Or8Way(in=zrj, out=zrn);
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Or8Way OR8F1(zri, zrm);
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Or8Way OR8F2(zrj, zrn);
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Or ORF1(zrm, zrn, zro);
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Not NOTF2(zro, zr);
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Mux MUXF2(1'b0, 1'b1, ngr, ng);
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// Or(a=zrm, b=zrn, out=zro);
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// Not(in=zro, out=zr);
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// Mux(a=false, b=true, sel=ngr, out=ng);
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endmodule
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