26 lines
351 B
Verilog
26 lines
351 B
Verilog
/**
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* Exclusive-or gate:
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* out = not (a == b)
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*/
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`default_nettype none
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module Xor(
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input a,
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input b,
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output out
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);
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// Put your code here:
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wire nota;
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wire notb;
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Not NOT1(a, nota);
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Not NOT2(b, notb);
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wire w1;
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wire w2;
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And AND1(a, notb, w1);
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And AND2(nota, b, w2);
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Or OR(w1, w2, out);
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endmodule
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