29 lines
487 B
Verilog
29 lines
487 B
Verilog
/**
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* 8-way Or:
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* out = (in[0] or in[1] or ... or in[7])
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*/
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`default_nettype none
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module Or8Way(
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input [7:0] in,
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output out
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);
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// Put your code here:
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wire outA;
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wire outB;
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wire outC;
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wire outD;
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wire outE;
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wire outF;
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Or OR0(in[0], in[1], outA);
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Or OR2(in[2], outA, outB);
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Or OR3(in[3], outB, outC);
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Or OR4(in[4], outC, outD);
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Or OR5(in[5], outD, outE);
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Or OR6(in[6], outE, outF);
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Or OR7(in[7], outF, out);
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endmodule
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