30 lines
661 B
Verilog
30 lines
661 B
Verilog
/**
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* 16-bit Not:
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* for i=0..15: out[i] = not in[i]
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*/
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`default_nettype none
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module Not16(
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input [15:0] in,
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output [15:0] out
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);
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// Put your code here:
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Not NOT0(in[0], out[0]);
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Not NOT1(in[1], out[1]);
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Not NOT2(in[2], out[2]);
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Not NOT3(in[3], out[3]);
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Not NOT4(in[4], out[4]);
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Not NOT5(in[5], out[5]);
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Not NOT6(in[6], out[6]);
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Not NOT7(in[7], out[7]);
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Not NOT8(in[8], out[8]);
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Not NOT9(in[9], out[9]);
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Not NOT10(in[10], out[10]);
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Not NOT11(in[11], out[11]);
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Not NOT12(in[12], out[12]);
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Not NOT13(in[13], out[13]);
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Not NOT14(in[14], out[14]);
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Not NOT15(in[15], out[15]);
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endmodule
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