39 lines
984 B
Verilog
39 lines
984 B
Verilog
/**
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* 16-bit multiplexor:
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* for i = 0..15 out[i] = a[i] if sel == 0
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* b[i] if sel == 1
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*/
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`default_nettype none
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module Mux8Way16(
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input [15:0] a,
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input [15:0] b,
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input [15:0] c,
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input [15:0] d,
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input [15:0] e,
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input [15:0] f,
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input [15:0] g,
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input [15:0] h,
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input [2:0] sel,
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output [15:0] out
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);
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// Put your code here:
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wire [15:0] outab;
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wire [15:0] outcd;
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wire [15:0] outef;
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wire [15:0] outgh;
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wire [15:0] outabcd;
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wire [15:0] outefgh;
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Mux16 MUX16A(a[15:0], b[15:0], sel[0], outab[15:0]);
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Mux16 MUX16B(c[15:0], d[15:0], sel[0], outcd[15:0]);
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Mux16 MUX16C(e[15:0], f[15:0], sel[0], outef[15:0]);
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Mux16 MUX16D(g[15:0], h[15:0], sel[0], outgh[15:0]);
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Mux16 MUX16E(outab[15:0], outcd[15:0], sel[1], outabcd[15:0]);
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Mux16 MUX16F(outef[15:0], outgh[15:0], sel[1], outefgh[15:0]);
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Mux16 MUX16(outabcd[15:0], outefgh[15:0], sel[2], out[15:0]);
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endmodule
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