33 lines
923 B
Verilog
33 lines
923 B
Verilog
/**
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* 16-bit multiplexor:
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* for i = 0..15 out[i] = a[i] if sel == 0
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* b[i] if sel == 1
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*/
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`default_nettype none
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module Mux16(
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input [15:0] a,
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input [15:0] b,
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input sel,
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output [15:0] out
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);
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// Put your code here:
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Mux MUX0(a[0], b[0], sel, out[0]);
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Mux MUX1(a[1], b[1], sel, out[1]);
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Mux MUX2(a[2], b[2], sel, out[2]);
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Mux MUX3(a[3], b[3], sel, out[3]);
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Mux MUX4(a[4], b[4], sel, out[4]);
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Mux MUX5(a[5], b[5], sel, out[5]);
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Mux MUX6(a[6], b[6], sel, out[6]);
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Mux MUX7(a[7], b[7], sel, out[7]);
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Mux MUX8(a[8], b[8], sel, out[8]);
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Mux MUX9(a[9], b[9], sel, out[9]);
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Mux MUX10(a[10], b[10], sel, out[10]);
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Mux MUX11(a[11], b[11], sel, out[11]);
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Mux MUX12(a[12], b[12], sel, out[12]);
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Mux MUX13(a[13], b[13], sel, out[13]);
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Mux MUX14(a[14], b[14], sel, out[14]);
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Mux MUX15(a[15], b[15], sel, out[15]);
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endmodule
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