28 lines
527 B
Verilog
28 lines
527 B
Verilog
/**
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* 4-way demultiplexor:
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* {a, b, c, d} = {in, 0, 0, 0} if sel == 00
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* {0, in, 0, 0} if sel == 01
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* {0, 0, in, 0} if sel == 10
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* {0, 0, 0, in} if sel == 11
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*/
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`default_nettype none
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module DMux4Way(
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input in,
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input [1:0] sel,
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output a,
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output b,
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output c,
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output d
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);
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// Put your code here:
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wire outx;
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wire outy;
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DMux DMUXA(in, sel[1], outx, outy);
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DMux DMUXB(outx, sel[0], a, b);
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DMux DMUXC(outy, sel[0], c, d);
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endmodule
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