31 lines
782 B
Verilog
31 lines
782 B
Verilog
/**
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* 16-bit bitwise And:
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* for i = 0..15: out[i] = (a[i] and b[i])
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*/
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`default_nettype none
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module And16(
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input [15:0] a,
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input [15:0] b,
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output [15:0] out
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);
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// Put your code here:
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And AND0(a[0], b[0], out[0]);
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And AND1(a[1], b[1], out[1]);
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And AND2(a[2], b[2], out[2]);
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And AND3(a[3], b[3], out[3]);
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And AND4(a[4], b[4], out[4]);
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And AND5(a[5], b[5], out[5]);
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And AND6(a[6], b[6], out[6]);
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And AND7(a[7], b[7], out[7]);
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And AND8(a[8], b[8], out[8]);
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And AND9(a[9], b[9], out[9]);
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And AND10(a[10], b[10], out[10]);
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And AND11(a[11], b[11], out[11]);
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And AND12(a[12], b[12], out[12]);
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And AND13(a[13], b[13], out[13]);
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And AND14(a[14], b[14], out[14]);
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And AND15(a[15], b[15], out[15]);
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endmodule
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