33 lines
1.2 KiB
Verilog
33 lines
1.2 KiB
Verilog
/*
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* LCD communicates with ILI9341V LCD controller over 4 wire SPI.
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*
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* When load=1 and in[8]=0 transmission of byte in[7:0] is initiated.
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* CSX is goes low (and stays low even when transmission is completed).
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* DCX is set to in[9]. The byte in[7:0] is send to SDO bitwise together
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* with 8 clock signals on SCK. During transmission out[15] is 1.
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* After 16 clock cycles transmission is completed and out[15] is set to 0.
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*
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* When load=1 and in[8]=1 CSX goes high and DCX=in[9] without transmission
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* of any bit.
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*
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* When load16=1 transmission of word in[15:0] is initiated. CSX is goes low
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* (and stays low even when transmission is completed). DCX is set to 1 (data).
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* After 32 clock cycles transmission is completed and out[15] is set to 0.
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*/
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`default_nettype none
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module LCD(
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input clk, //clock 25 MHz
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input load, //start send command/byte over SPI
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input load16, //start send data (16 bits)
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input [15:0] in, //data to be send
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output [15:0] out, //data to be send
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output DCX, //SPI data/command not
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output CSX, //SPI chip select not
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output SDO, //SPI serial data out
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output SCK //SPI serial clock
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);
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// Put your code here:
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endmodule
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