90 lines
1.9 KiB
Verilog
90 lines
1.9 KiB
Verilog
`timescale 10ns/1ns
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`default_nettype none
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module LCD_tb();
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// IN,OUT
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reg clk = 0;
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reg load = 0;
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reg load16 = 0;
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reg [15:0] in = 0;
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wire [15:0] out;
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wire DCX;
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wire CSX;
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wire SDO;
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wire SCK;
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// Part
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LCD LCD(
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.clk(clk),
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.load(load),
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.load16(load16),
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.in(in),
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.out(out),
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.DCX(DCX), //SPI-line data/command not
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.CSX(CSX), //SPI-line chip enabled not
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.SDO(SDO), //SPI-Line master out slave in
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.SCK(SCK) //SPI-clock
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);
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// Simulate
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always #2 clk=~clk;
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wire trigger;
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assign trigger = (n==20) || (n==40) || (n==60) || (n==80) || (n==100);
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reg [1:0] xx=0;
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always @(posedge clk) begin
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in <= trigger?$random&16'h02ff:in;
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if (trigger) xx<=xx+1;
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load <= trigger&&(~xx[1]);
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load16 <= trigger&&(xx==2);
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end
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// Compare
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reg[5:0] bits=0;
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reg d16=0;
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always @(posedge clk)
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d16 <= load16?1:(load)?0:d16;
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always @(posedge clk)
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bits <= (load&~in[8]|load16)?1:(((bits[4]&~d16)|bits[5])?0:(busy?bits+1:0));
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wire busy=|bits;
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wire out_cmp = busy;
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reg [15:0] shift=0;
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always @(posedge clk)
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shift <= (load|load16)?in:(~SCK_cmp?shift:{shift[14:0],1'b0});
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wire SCK_cmp=busy&~bits[0];
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reg ce_cmp=0;
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always @(posedge clk)
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ce_cmp<=(load|load16)?(load16|load&~in[8]):ce_cmp;
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wire CSX_cmp=~ce_cmp;
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reg DCX_cmp=0;
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always @(posedge clk)
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DCX_cmp<=load?in[9]:(load16)?1:DCX_cmp;
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wire SDO_cmp=(d16&shift[15])|(~d16&shift[7]);
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reg fail = 0;
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reg [31:0] n = 0;
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task check;
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#4
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if ((out[15]!=out_cmp)||(SDO!=SDO_cmp)||(CSX!=CSX_cmp)||(SCK!=SCK_cmp)||(DCX!=DCX_cmp))
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begin
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$display("FAIL: clk=%1b, load=%1b, in=%16b, out=%16b, DCX=%1b, CSX=%1b, SDO=%1b, SCK=%1b",clk,load,in,out,DCX,CSX,SDO,SCK);
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fail=1;
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end
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endtask
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initial begin
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$dumpfile("LCD_tb.vcd");
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$dumpvars(0, LCD_tb);
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$display("------------------------");
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$display("Testbench: LCD");
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for (n=0; n<400;n=n+1)
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check();
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if (fail==0) $display("passed");
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$display("------------------------");
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$finish;
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end
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endmodule
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