75 lines
1.4 KiB
Verilog
75 lines
1.4 KiB
Verilog
`timescale 10ns/1ns
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`default_nettype none
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module UartTX_tb();
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// IN,OUT
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reg clk = 0;
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reg load = 0;
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reg [15:0] in = 0;
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wire TX;
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wire [15:0] out;
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// Part
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UartTX UartTX(
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.clk(clk),
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.load(load),
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.in(in),
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.TX(TX),
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.out(out)
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);
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// Simulate
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always #2 clk=~clk;
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wire trigger;
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assign trigger = (n==1000) || (n==5000) || (n==9000);
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always @(posedge clk) begin
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in <= trigger?$random:in;
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load <= trigger;
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end
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// Compare
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reg [9:0] uart=10'b1111111111;
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reg [15:0] baudrate = 0;
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reg [15:0] bits = 0;
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wire is216=(baudrate==216);
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reg [15:0] out_cmp=0;
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always @(posedge clk)
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out_cmp <=load?16'h8000:(bits==9)&is216?16'd0:out_cmp;
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always @(posedge clk)
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bits <= (load)?0:is216?bits+1:bits;
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always @(posedge clk)
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baudrate <= (is216?0:out_cmp?baudrate+1:baudrate);
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always @(posedge clk)
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uart <= (load)?((in<<2)|1):(is216?{1'b1,uart[9:1]}:uart);
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wire TX_cmp;
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assign TX_cmp = uart[1];
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reg fail = 0;
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reg [31:0] n = 0;
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task check;
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#4
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if ((TX != TX_cmp) ||(out != out_cmp))
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begin
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$display("FAIL: clk=%1b, load=%1b, in=%16b, out=%16b, TX=%1b",clk,load,in,out,TX);
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fail=1;
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end
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endtask
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initial begin
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$dumpfile("UartTX_tb.vcd");
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$dumpvars(0, UartTX_tb);
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$display("------------------------");
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$display("Testbench: UartTX");
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for (n=0; n<13000;n=n+1)
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check();
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if (fail==0) $display("passed");
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$display("------------------------");
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$finish;
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end
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endmodule
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