nand2/03_Sequential_Logic/BitShift8L.v

63 lines
1.8 KiB
Verilog

/**
* 8-bit Shiftregister (shifts to left)
* if (load == 1) out[t+1] = in[t]
* else if (shift == 1) out[t+1] = out[t]<<1 | inLSB
* (shift one position to left and insert inLSB as least significant bit)
*/
`default_nettype none
module BitShift8L(
input clk,
input [7:0] in,
input inLSB,
input load,
input shift,
output [7:0] out
);
// Put your code here:
reg [7:0] reg8;
always @(posedge clk) begin
if (load == 1) begin
reg8[7:0] = in[7:0];
end
else if (shift == 1 ) begin
reg8[7:1] = reg8[6:0];
reg8[0] = inLSB;
end
end
assign out = reg8;
// wire [7:0] out_l;
// wire [7:0] out_s;
// Mux MUXLA(out[0], in[0], load, out_l[0]);
// Mux MUXLB(out[1], in[1], load, out_l[1]);
// Mux MUXLC(out[2], in[2], load, out_l[2]);
// Mux MUXLD(out[3], in[3], load, out_l[3]);
// Mux MUXLE(out[4], in[4], load, out_l[4]);
// Mux MUXLF(out[5], in[5], load, out_l[5]);
// Mux MUXLG(out[6], in[6], load, out_l[6]);
// Mux MUXLH(out[7], in[7], load, out_l[7]);
// Mux MUXSA(out_l[0], inLSB, shift, out_s[0]);
// Mux MUXSB(out_l[1], out[0], shift, out_s[1]);
// Mux MUXSC(out_l[2], out[1], shift, out_s[2]);
// Mux MUXSD(out_l[3], out[2], shift, out_s[3]);
// Mux MUXSE(out_l[4], out[3], shift, out_s[4]);
// Mux MUXSF(out_l[5], out[4], shift, out_s[5]);
// Mux MUXSG(out_l[6], out[5], shift, out_s[6]);
// Mux MUXSH(out_l[7], out[6], shift, out_s[7]);
// Bit BITA(clk, out_s[0], 1'b1, out[0]);
// Bit BITB(clk, out_s[1], 1'b1, out[1]);
// Bit BITC(clk, out_s[2], 1'b1, out[2]);
// Bit BITD(clk, out_s[3], 1'b1, out[3]);
// Bit BITE(clk, out_s[4], 1'b1, out[4]);
// Bit BITF(clk, out_s[5], 1'b1, out[5]);
// Bit BITG(clk, out_s[6], 1'b1, out[6]);
// Bit BITH(clk, out_s[7], 1'b1, out[7]);
endmodule