62 lines
1.0 KiB
Verilog
62 lines
1.0 KiB
Verilog
`default_nettype none
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module BitShift8L_tb();
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// IN,OUT
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reg clk=1;
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reg [7:0] in;
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reg load,shift,inLSB;
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wire [7:0] out;
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// Part
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BitShift8L BITSHIFT8L(
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.clk(clk),
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.in(in),
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.inLSB(inLSB),
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.load(load),
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.shift(shift),
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.out(out)
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);
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// Simulate
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always #1 clk=~clk;
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always @(posedge clk) begin
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in <= $random;
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shift <= (n==0) || ((n>20) && (n<50));
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inLSB <= $random;
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load <= (n==10);
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end
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// Compare
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reg [7:0] out_cmp;
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always @(posedge clk)
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out_cmp <= load?in:(shift?(out_cmp<<1)|inLSB:out_cmp);
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reg fail = 0;
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reg [15:0] n = 0;
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task check;
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#1
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if (out != out_cmp)
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begin
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$display("FAIL: clk=%1b, in=%8b, load=%1b, shift=%1b, out=%8b",clk,in,inLSB,load,shift,out);
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fail=1;
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end
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endtask
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// Test
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initial begin
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$dumpfile("BitShift8L_tb.vcd");
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$dumpvars(0, BitShift8L_tb);
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$display("------------------------");
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$display("Testbench: BitShift8L");
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for (n=0; n<1000;n=n+1)
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check();
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if (fail==0) $display("passed");
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$display("------------------------");
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$finish;
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end
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endmodule
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