82 lines
1.9 KiB
Verilog
82 lines
1.9 KiB
Verilog
`default_nettype none
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module ALU_tb();
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// IN,OUT
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reg [15:0] x,y;
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reg zx,nx,zy,ny,f,no;
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wire [15:0] out;
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wire zr,ng;
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// Part
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ALU ALU(
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.x(x),
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.y(y),
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.zx(zx),
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.nx(nx),
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.zy(zy),
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.ny(ny),
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.f(f),
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.no(no),
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.out(out),
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.zr(zr),
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.ng(ng)
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);
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// Compare
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wire [15:0] xx,yy,out_cmp;
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wire zr_cmp,ng_cmp;
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assign xx = nx?(zx?~0:~x):(zx?0:x);
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assign yy = ny?(zy?~0:~y):(zy?0:y);
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assign out_cmp= no?(f?~(xx+yy):~(xx&yy)):(f?(xx+yy):(xx&yy));
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assign zr_cmp = (out==0);
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assign ng_cmp = out[15];
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reg fail = 0;
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reg [15:0] n = 0;
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task check;
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#1
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if ((out != out_cmp) || (zr != zr_cmp) || (ng != ng_cmp))
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begin
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$display("FAIL: x=%16b, y=%16b, zx=%1b, nx=%1b, zy=%1b, ny=%1b, f=%1b, no=%1b, out=%16b, zr=%1b, ng=%1b",x,y,zx,nx,zy,ny,f,no,out,zr,ng);
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fail=1;
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end
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endtask
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initial begin
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$dumpfile("ALU_tb.vcd");
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$dumpvars(0, ALU_tb);
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$display("------------------------");
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$display("Testbench: ALU");
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for (n=0; n<100;n=n+1)
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begin
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x=$random;
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y=$random;
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zx=1;nx=0;zy=1;ny=0;f=1;no=0;check();// 0
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zx=1;nx=1;zy=1;ny=1;f=1;no=1;check();// 1
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zx=1;nx=1;zy=1;ny=0;f=1;no=0;check();// -1
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zx=0;nx=0;zy=1;ny=1;f=0;no=0;check();// x
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zx=1;nx=1;zy=0;ny=0;f=0;no=0;check();// y
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zx=0;nx=0;zy=1;ny=1;f=0;no=1;check();// !x
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zx=1;nx=1;zy=0;ny=0;f=0;no=1;check();// !y
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zx=0;nx=0;zy=1;ny=1;f=1;no=1;check();// -x
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zx=1;nx=1;zy=0;ny=0;f=1;no=1;check();// -y
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zx=0;nx=1;zy=1;ny=1;f=1;no=1;check();// x+1
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zx=1;nx=1;zy=0;ny=1;f=1;no=1;check();// y+1
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zx=0;nx=0;zy=1;ny=1;f=1;no=0;check();// x-1
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zx=1;nx=1;zy=0;ny=0;f=1;no=0;check();// y-1
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zx=0;nx=0;zy=0;ny=0;f=1;no=0;check();// x+y
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zx=0;nx=1;zy=0;ny=0;f=1;no=1;check();// x-y
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zx=0;nx=0;zy=0;ny=1;f=1;no=1;check();// y-x
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zx=0;nx=0;zy=0;ny=0;f=0;no=0;check();// x&y
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zx=0;nx=1;zy=0;ny=1;f=0;no=1;check();// x|y
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end
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if (fail==0) $display("passed");
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$display("------------------------");
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$finish;
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end
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endmodule
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