52 lines
753 B
Verilog
52 lines
753 B
Verilog
`default_nettype none
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module Inc16_tb();
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// IN,OUT
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reg [15:0] in;
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wire [15:0] out;
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// Part
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Inc16 INC16(
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.in(in),
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.out(out)
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);
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// Compare
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wire [15:0] out_cmp;
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assign out_cmp = in+1;
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reg fail = 0;
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reg [15:0] n=0;
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task check;
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#1
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if (out != out_cmp)
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begin
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$display("FAIL: in=%16b, out=%16b",in,out);
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fail=1;
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end
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endtask
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// Test
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initial begin
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$dumpfile("Inc16_tb.vcd");
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$dumpvars(0, Inc16_tb);
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$display("------------------------");
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$display("Testbench: Inc16");
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in=0;check();
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in=16'b1111111111111111;check();
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for (n=0; n<1000;n=n+1)
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begin
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in=$random;
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check();
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end
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if (fail==0) $display("passed");
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$display("------------------------");
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$finish;
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end
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endmodule
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