nand2/01_Boolean_Logic/Mux8Way16.v

39 lines
984 B
Verilog

/**
* 16-bit multiplexor:
* for i = 0..15 out[i] = a[i] if sel == 0
* b[i] if sel == 1
*/
`default_nettype none
module Mux8Way16(
input [15:0] a,
input [15:0] b,
input [15:0] c,
input [15:0] d,
input [15:0] e,
input [15:0] f,
input [15:0] g,
input [15:0] h,
input [2:0] sel,
output [15:0] out
);
// Put your code here:
wire [15:0] outab;
wire [15:0] outcd;
wire [15:0] outef;
wire [15:0] outgh;
wire [15:0] outabcd;
wire [15:0] outefgh;
Mux16 MUX16A(a[15:0], b[15:0], sel[0], outab[15:0]);
Mux16 MUX16B(c[15:0], d[15:0], sel[0], outcd[15:0]);
Mux16 MUX16C(e[15:0], f[15:0], sel[0], outef[15:0]);
Mux16 MUX16D(g[15:0], h[15:0], sel[0], outgh[15:0]);
Mux16 MUX16E(outab[15:0], outcd[15:0], sel[1], outabcd[15:0]);
Mux16 MUX16F(outef[15:0], outgh[15:0], sel[1], outefgh[15:0]);
Mux16 MUX16(outabcd[15:0], outefgh[15:0], sel[2], out[15:0]);
endmodule