nand2/01_Boolean_Logic/And16.v

31 lines
782 B
Verilog

/**
* 16-bit bitwise And:
* for i = 0..15: out[i] = (a[i] and b[i])
*/
`default_nettype none
module And16(
input [15:0] a,
input [15:0] b,
output [15:0] out
);
// Put your code here:
And AND0(a[0], b[0], out[0]);
And AND1(a[1], b[1], out[1]);
And AND2(a[2], b[2], out[2]);
And AND3(a[3], b[3], out[3]);
And AND4(a[4], b[4], out[4]);
And AND5(a[5], b[5], out[5]);
And AND6(a[6], b[6], out[6]);
And AND7(a[7], b[7], out[7]);
And AND8(a[8], b[8], out[8]);
And AND9(a[9], b[9], out[9]);
And AND10(a[10], b[10], out[10]);
And AND11(a[11], b[11], out[11]);
And AND12(a[12], b[12], out[12]);
And AND13(a[13], b[13], out[13]);
And AND14(a[14], b[14], out[14]);
And AND15(a[15], b[15], out[15]);
endmodule