/**
 * UartRX receives bytes over UART
 *
 * When clear = 1 the chip clears the receive buffer and is ready to receive
 * next byte. out[15] is set to 1 to show, that chip is ready to receive next
 * byte. When RX goes low the chip starts sampling the RX line. After reading
 * of byte completes, chip ouputs the received byte to out[7:0]] with out[15]=0.
 */
`default_nettype none

module UartRX(
    input clk,
    input clear,
    input RX,
    output reg [15:0] out
);

    // Put your code here:
    wire clkdRX;
    reg active=0;
    reg [8:0] uart;
    reg [11:0] is108;
    reg [11:0] is216;
    always @(posedge clk) begin
        out <= clear ? 16'h8000 : out;

        if ((active==0) && (RX == 0)) begin
            active <= 1;
            is216 <= 1;
            uart <= 0;
        end
        else if (active==1) begin
            if (is216 == 2169) begin
                active <= 0;
                out <= {8'b0, uart};
            end
            else begin
                is216 <= is216 + 1;
                is108 <= is216 / 108;
                case (is108)
                    3  : uart[0] <= clkdRX;
                    5  : uart[1] <= clkdRX;
                    7  : uart[2] <= clkdRX;
                    9  : uart[3] <= clkdRX;
                    11 : uart[4] <= clkdRX;
                    13 : uart[5] <= clkdRX;
                    15 : uart[6] <= clkdRX;
                    17 : uart[7] <= clkdRX;
                endcase
            end
        end
    end

    DFF DFF(clk, RX, clkdRX);
endmodule