/**
 * SRAM controller:
 * If load[t] == 1 then out[t+1] = in[t]
 *                      OEX[t+1] = 1
 *                      WEX[t+1] = 0
 *                      DATA[t+1] = in[t] (DATA is configured as output)
 * At any other time:
 * out = DATA (DATA is configured as input)
 * CSX =0;
 */
`default_nettype none
module SRAM_D(
    input clk,
    input load,
    input [15:0] in,
    output [15:0] out,
    inout [15:0] DATA,  // SRAM data 16 Bit
    output reg CSX=0,         // SRAM chip_enable_not
    output reg OEX,     // SRAM output_enable_not
    output reg WEX      // SRAM write_enable_not
);

    // Put your code here:
    reg [15:0] to_sram;
    always @(posedge clk) begin
        if (load) begin
            OEX <= 1;
            WEX <= 0;
            to_sram <= in;
        end else begin
            OEX <= 0;
            WEX <= 1;
        end
    end
    // wire LOAD;
    // wire [15:0] to_sram;
    // assign CSX = 0;
    // assign OEX = (LOAD) ? 1 : 0;
    // assign WEX = (LOAD) ? 0 : 1;
    // DFF DFF(clk, load, LOAD);
    // Register Register(clk, in, load, to_sram);
    InOut InOut(DATA, to_sram, out, OEX);
    //if (dir == 0) IN: PIN are set to High-Z, dataR = external PIN
    //if (dir == 1) OUTPUT: dataW is output to external PIN, dataR = dataW


endmodule