/**
 * The ALU (Arithmetic Logic Unit).
 * Computes one of the following functions:
 * x+y, x-y, y-x, 0, 1, -1, x, y, -x, -y, !x, !y,
 * x+1, y+1, x-1, y-1, x&y, x|y on two 16-bit inputs,
 * according to 6 input bits denoted zx,nx,zy,ny,f,no.
 * In addition, the ALU computes two 1-bit outputs:
 * if the ALU output == 0, zr is set to 1; otherwise zr is set to 0;
 * if the ALU output < 0, ng is set to 1; otherwise ng is set to 0.
 */

// Implementation: the ALU logic manipulates the x and y inputs
// and operates on the resulting values, as follows:
// if (zx == 1) set x = 0        // 16-bit constant
// if (nx == 1) set x = !x       // bitwise not
// if (zy == 1) set y = 0        // 16-bit constant
// if (ny == 1) set y = !y       // bitwise not
// if (f == 1)  set out = x + y  // integer 2's complement addition
// if (f == 0)  set out = x & y  // bitwise and
// if (no == 1) set out = !out   // bitwise not
// if (out == 0) set zr = 1
// if (out < 0) set ng = 1

`default_nettype none
module ALU(
    input [15:0] x,     // input x (16 bit)
    input [15:0] y,     // input y (16 bit)
    input zx,               // zero the x input?
    input nx,               // negate the x input?
    input zy,               // zero the y input?
    input ny,               // negate the y input?
    input f,                // compute out = x + y (if 1) or x & y (if 0)
    input no,               // negate the out output?
    output [15:0] out,      // 16-bit output
    output zr,              // 1 if (out == 0), 0 otherwise
    output ng               // 1 if (out < 0),  0 otherwise
);

    // Put your code here:
    wire [15:0] xa;
    wire [15:0] xb;
    wire [15:0] xc;
    wire [15:0] ya;
    wire [15:0] yb;
    wire [15:0] yc;
    wire [15:0] xandy;
    wire [15:0] xplusy;
    wire [15:0] xf;
    wire [15:0] xn;
    wire [7:0] zri;
    wire [7:0] zrj;
    wire ngr;
    wire zrm;
    wire zrn;
    wire zro;
    wire tt;
    wire ff;

    // Mux16(a=x, b=false, sel=zx, out=xa);
    // Not16(in=xa, out=xb);
    // Mux16(a=xa, b=xb, sel=nx, out=xc);
    Mux16 MUXX1(x, 16'b0, zx, xa);
    Not16 NOTX1(xa, xb);
    Mux16 MUXX2(xa, xb, nx, xc);

    // Mux16(a=y, b=false, sel=zy, out=ya);
    // Not16(in=ya, out=yb);
    // Mux16(a=ya, b=yb, sel=ny, out=yc);
    Mux16 MUXY1(y, 16'b0, zy, ya);
    Not16 NOTY1(ya, yb);
    Mux16 MUXY2(ya, yb, ny, yc);

    // And16(a=xc, b=yc, out=xandy);
    // Add16(a=xc, b=yc, out=xplusy);
    // Mux16(a=xandy, b=xplusy, sel=f, out=xf);
    And16 ANDZ1(xc, yc, xandy);
    Add16 ADDZ1(xc, yc, xplusy);
    Mux16 MUXZ1(xandy, xplusy, f, xf);

    // Not16(in=xf, out=xn);
    // Mux16(a=xf, b=xn, sel=no, out=out, out[15]=ngr, out[0..7]=zri, out[8..15]=zrj);
    Not16 NOTF1(xf, xn);
    Mux16 MUXF1(xf, xn, no, out);

    assign ngr = out[15];
    assign zri[7:0] = out[7:0];
    assign zrj[7:0] = out[15:8];

    // Or8Way(in=zri, out=zrm);
    // Or8Way(in=zrj, out=zrn);
    Or8Way OR8F1(zri, zrm);
    Or8Way OR8F2(zrj, zrn);
    Or ORF1(zrm, zrn, zro);
    Not NOTF2(zro, zr);
    Mux MUXF2(1'b0, 1'b1, ngr,  ng);
    // Or(a=zrm, b=zrn, out=zro);
    // Not(in=zro, out=zr);
    // Mux(a=false, b=true, sel=ngr, out=ng);

endmodule