/** * Or gate: * out = 1 if (a == 1 or b == 1) * 0 otherwise */ `default_nettype none module Or( input a, input b, output out ); // Put your code here: wire nanda; wire nandb; Nand NAND1(a, a, nanda); Nand NAND2(b, b, nandb); Nand NAND3(nanda, nandb, out); endmodule