/*
 * LCD communicates with ILI9341V LCD controller over 4 wire SPI.
 * 
 * When load=1 and in[8]=0 transmission of byte in[7:0] is initiated.
 * CSX is goes low (and stays low even when transmission is completed).
 * DCX is set to in[9]. The byte in[7:0] is send to SDO bitwise together
 * with 8 clock signals on SCK. During transmission out[15] is 1.
 * After 16 clock cycles transmission is completed and out[15] is set to 0.
 * 
 * When load=1 and in[8]=1 CSX goes high and DCX=in[9] without transmission
 * of any bit.
 * 
 * When load16=1 transmission of word in[15:0] is initiated. CSX is goes low
 * (and stays low even when transmission is completed). DCX is set to 1 (data).
 * After 32 clock cycles transmission is completed and out[15] is set to 0.
*/
`default_nettype none
module LCD(
        input clk,         //clock 25 MHz
        input load,        //start send command/byte over SPI
        input load16,      //start send data (16 bits)
        input [15:0] in,   //data to be send
        output reg [15:0] out, //data to be send
        output reg DCX,        //SPI data/command not
        output reg CSX,        //SPI chip select not
        output reg SDO,        //SPI serial data out
        output reg SCK         //SPI serial clock
);

    // Put your code here:
    reg [15:0] to_send;
    reg [3:0] nthbit=0;
    reg csx_low=0;
    reg is_data=0;
    reg active=0;
    reg active16=0;
    reg [4:0] is16;
    always @(posedge clk) begin
        SDO <= 0;
        SCK <= 0;
        CSX <= (csx_low) ? 0 : 1;
        DCX <= (is_data) ? 1 : 0;
        out <= (load || load16 || active || active16) ? 16'h8000 : 16'h0000;

        if (load && ~active && ~active16) begin
            if (in[8]) begin
                csx_low <= 0;
                CSX <= 1;
            end else begin
                active <= 1;
                is16 <= 1;
                csx_low <= 1;
                CSX <= 0;
                is_data <= in[9];
                DCX <= in[9];
                to_send <= in;
                SDO <= in[7];
            end
        end
        else if (load16 && ~active && ~active16) begin
                active16 <= 1;
                is16 <= 1;
                csx_low <= 1;
                to_send <= in;
                SDO <= in[15];
        end
        else if (active) begin
            SCK <= ~SCK;
            if ( is16 == 15) begin
                active <= 0;
                SDO <= to_send[0];
            end
            else begin
                is16 <=  is16 + 1;
                SDO <= SDO;
                case (is16)
                    2  : SDO <= to_send[6];
                    4  : SDO <= to_send[5];
                    6  : SDO <= to_send[4];
                    8  : SDO <= to_send[3];
                    10 : SDO <= to_send[2];
                    12 : SDO <= to_send[1];
                    14 : SDO <= to_send[0];
                 endcase

            end
        end
        else if (active16) begin
            SCK <= ~SCK;
            if ( is16 == 31) begin
                active16 <= 0;
                SDO <= to_send[0];
            end
            else begin
                is16 <=  is16 + 1;
                SDO <= SDO;
                case (is16)
                    2  : SDO <= to_send[14];
                    4  : SDO <= to_send[13];
                    6  : SDO <= to_send[12];
                    8  : SDO <= to_send[11];
                    10 : SDO <= to_send[10];
                    12 : SDO <= to_send[9];
                    14 : SDO <= to_send[8];
                    16 : SDO <= to_send[7];
                    18 : SDO <= to_send[6];
                    20 : SDO <= to_send[5];
                    22 : SDO <= to_send[4];
                    24 : SDO <= to_send[3];
                    26 : SDO <= to_send[2];
                    28 : SDO <= to_send[1];
                    30 : SDO <= to_send[0];
                 endcase

            end
        end
    end


endmodule