/**
 * UartRX receives bytes over UART
 *
 * When clear = 1 the chip clears the receive buffer and is ready to receive
 * next byte. out[15] is set to 1 to show, that chip is ready to receive next
 * byte. When RX goes low the chip starts sampling the RX line. After reading
 * of byte completes, chip ouputs the received byte to out[7:0]] with out[15]=0.
 */
`default_nettype none
module UartRX(
    input clk,
    input clear,
    input RX,
    output reg [15:0] out
);

    // Put your code here:
    wire clkdRX;
    reg active=0;
    reg [7:0] uart;
    reg [3:0] nthbit;
    reg [11:0] is216;
    always @(posedge clk) begin
        out <= clear ? 16'h8000 : out;

        if ((active==0) && (RX == 0)) begin
            active <= 1;
            is216 <= 1;
            uart <= 0;
            nthbit <= 0;
        end
        else if (active==1) begin
            is216 <= (is216 == 216) ? 0 : is216 + 1;
            nthbit <= (is216 == 108) ? nthbit + 1 : nthbit;
            case (nthbit)
                1 : uart[0] <= RX;
                2 : uart[1] <= RX;
                3 : uart[2] <= RX;
                4 : uart[3] <= RX;
                5 : uart[4] <= RX;
                6 : uart[5] <= RX;
                7 : uart[6] <= RX;
                8 : uart[7] <= RX;
            endcase
            if (nthbit == 10 && is216 == 216) begin
                active <= 0;
                out <= {8'b0, uart};
            end
        end
    end
endmodule