diff --git a/06_IO_Devices/GO.v b/06_IO_Devices/GO.v index 0753329..f3ac9f2 100644 --- a/06_IO_Devices/GO.v +++ b/06_IO_Devices/GO.v @@ -14,5 +14,13 @@ module GO( ); // Put your code here: - + reg active=0; + always @(posedge clk) begin + if (load) begin + active = 1; + end + end + + assign instruction = (active) ? sram_data : ROM_data; + assign SRAM_ADDR = (active) ? pc : sram_addr; endmodule diff --git a/06_IO_Devices/SPI.v b/06_IO_Devices/SPI.v index 0a9bef5..76b0ca5 100644 --- a/06_IO_Devices/SPI.v +++ b/06_IO_Devices/SPI.v @@ -9,16 +9,120 @@ `default_nettype none module SPI( - input clk, - input load, - input [15:0] in, - output [15:0] out, - output CSX, - output SDO, - input SDI, - output SCK + input clk, + input load, + input [15:0] in, + output reg [15:0] out, + output reg CSX, + output reg SDO, + input SDI, + output reg SCK ); - // Put your code here: + // Put your code here: + // 1100 0000 0101 1011 + // 1000 0000 0101 1011 + reg temp; + reg active=0; + reg [7:0] totx; + reg [7:0] torx; + reg [11:0] is216; + always @(posedge clk) begin + CSX <= 0; + SDO <= 0; + SCK <= 0; + out <= (out)? out : 0; + if (load == 1) begin + out[14:8] <= 0; + out[7:0] <= in[7:0]; + if (in[8]==1) begin + out[15] <= 0; + CSX <= 1; + end + else if (in[8]==0) begin + out[15] <= 1; + CSX <= 0; + active <= 1; + is216 <= 1; + totx[7:0] <= in[7:0]; + SDO <= in[7]; + //out <= (out<<1); + //out[0] <= SDI; + //torx[7] <= SDI; + end + end + else if (active==1) begin + SCK <= ~SCK; + if (is216 == 16) begin + active <= 0; + CSX <= CSX; + out <= {8'b0, torx[7:0]}; + end + else begin + CSX <= 0; + is216 <= is216 + 1; + //SDO <= totx[7-(is216/2)]; + torx[7-(is216/2)] <= SDI; + case (is216+1) + 2 : SDO <= totx[7]; + 3 : SDO <= totx[6]; + 4 : SDO <= totx[6]; + 5 : SDO <= totx[5]; + 6 : SDO <= totx[5]; + 7 : SDO <= totx[4]; + 8 : SDO <= totx[4]; + 9 : SDO <= totx[3]; + 10 : SDO <= totx[3]; + 11 : SDO <= totx[2]; + 12 : SDO <= totx[2]; + 13 : SDO <= totx[1]; + 14 : SDO <= totx[1]; + 15 : SDO <= totx[0]; + 16 : SDO <= totx[0]; + endcase + + // case (is216) + // 3 : torx[6] <= SDI; + // 5 : torx[5] <= SDI; + // 7 : torx[4] <= SDI; + // 9 : torx[3] <= SDI; + // 11 : torx[2] <= SDI; + // 13 : torx[1] <= SDI; + // 15 : torx[0] <= SDI; + // endcase + case (is216) + 2 : out <= (out<<1); + 4 : out <= (out<<1); + 6 : out <= (out<<1); + 8 : out <= (out<<1); + 10 : out <= (out<<1); + 12 : out <= (out<<1); + 14 : out <= (out<<1); + endcase + case (is216) + 2 : out[0] <= torx[7]; + 4 : out[0] <= torx[6]; + 6 : out[0] <= torx[5]; + 8 : out[0] <= torx[4]; + 10 : out[0] <= torx[3]; + 12 : out[0] <= torx[2]; + 14 : out[0] <= torx[1]; + endcase + case (is216) + 2 : out[15:8] <= {8'b10000000}; + 4 : out[15:8] <= {8'b10000000}; + 6 : out[15:8] <= {8'b10000000}; + 8 : out[15:8] <= {8'b10000000}; + 10 : out[15:8] <= {8'b10000000}; + 12 : out[15:8] <= {8'b10000000}; + 14 : out[15:8] <= {8'b10000000}; + endcase + end + end else begin + CSX <= CSX; + out <= out? out : 16'b0; + end + end endmodule + diff --git a/06_IO_Devices/SRAM_D.v b/06_IO_Devices/SRAM_D.v index c4bd8ac..fef2fc5 100644 --- a/06_IO_Devices/SRAM_D.v +++ b/06_IO_Devices/SRAM_D.v @@ -10,16 +10,33 @@ */ `default_nettype none module SRAM_D( - input clk, - input load, - input [15:0] in, - output [15:0] out, - inout [15:0] DATA, // SRAM data 16 Bit - output CSX, // SRAM chip_enable_not - output OEX, // SRAM output_enable_not - output WEX // SRAM write_enable_not + input clk, + input load, + input [15:0] in, + output [15:0] out, + inout [15:0] DATA, // SRAM data 16 Bit + output CSX, // SRAM chip_enable_not + output reg OEX, // SRAM output_enable_not + output reg WEX // SRAM write_enable_not ); - - // Put your code here: + + // Put your code here: + reg [15:0] to_sram; + always @(posedge clk) begin + if (load) begin + OEX <= 1; + WEX <= 0; + to_sram <= in; + end else begin + OEX <= 0; + WEX <= 1; + end + end + //DFF DFF(clk, load, LOAD); + //Register Register(clk, in, load, to_sram); + // assign OEX = (LOAD) ? 1 : 0; + // assign WEX = (LOAD) ? 0 : 1; + assign CSX = 0; + InOut InOut(DATA, to_sram, out, OEX); endmodule diff --git a/06_IO_Devices/UartRX.v b/06_IO_Devices/UartRX.v index 8d5285b..6177ca1 100644 --- a/06_IO_Devices/UartRX.v +++ b/06_IO_Devices/UartRX.v @@ -9,12 +9,47 @@ `default_nettype none module UartRX( - input clk, - input clear, - input RX, - output [15:0] out + input clk, + input clear, + input RX, + output reg [15:0] out ); - - // Put your code here: + // Put your code here: + wire clkdRX; + reg active=0; + reg [8:0] uart; + reg [11:0] is108; + reg [11:0] is216; + always @(posedge clk) begin + out <= clear ? 16'h8000 : out; + + if ((active==0) && (RX == 0)) begin + active <= 1; + is216 <= 1; + uart <= 0; + end + else if (active==1) begin + if (is216 == 2169) begin + active <= 0; + out <= {8'b0, uart}; + end + else begin + is216 <= is216 + 1; + is108 <= is216 / 108; + case (is108) + 3 : uart[0] <= clkdRX; + 5 : uart[1] <= clkdRX; + 7 : uart[2] <= clkdRX; + 9 : uart[3] <= clkdRX; + 11 : uart[4] <= clkdRX; + 13 : uart[5] <= clkdRX; + 15 : uart[6] <= clkdRX; + 17 : uart[7] <= clkdRX; + endcase + end + end + end + + DFF DFF(clk, RX, clkdRX); endmodule diff --git a/06_IO_Devices/UartTX.v b/06_IO_Devices/UartTX.v index 04532a7..683d334 100644 --- a/06_IO_Devices/UartTX.v +++ b/06_IO_Devices/UartTX.v @@ -9,13 +9,49 @@ */ `default_nettype none module UartTX( - input clk, - input load, - input [15:0] in, - output TX, - output [15:0] out + input clk, + input load, + input [15:0] in, + output TX, + output reg [15:0] out ); - // Put your code here: + // Put your code here: + reg uart=1; + reg active=0; + reg [3:0] nthbit=0; + reg [11:0] is216; + always @(posedge clk) begin + out <= (load || active) ? 16'h8000 : 16'h0000; + + if ((active==0) && (load == 1)) begin + active <= 1; + is216 <= 1; + uart <= 0; + end + else if (active==1) begin + if (is216 == 2170) begin + active <= 0; + out <= 16'h0000; + end + else begin + is216 <= is216 + 1; + nthbit <= (is216 + 1) / 217; + case (nthbit) + 0 : uart <= 0; + 1 : uart <= in[nthbit-1]; + 2 : uart <= in[nthbit-1]; + 3 : uart <= in[nthbit-1]; + 4 : uart <= in[nthbit-1]; + 5 : uart <= in[nthbit-1]; + 6 : uart <= in[nthbit-1]; + 7 : uart <= in[nthbit-1]; + 8 : uart <= in[nthbit-1]; + 9 : uart <= 1; + endcase + end + end + end + assign TX = uart; endmodule