diff --git a/06_IO_Devices/01_UartTX/hello.asm b/06_IO_Devices/01_UartTX/hello.asm index a1fb9a3..60d584e 100644 --- a/06_IO_Devices/01_UartTX/hello.asm +++ b/06_IO_Devices/01_UartTX/hello.asm @@ -2,31 +2,117 @@ // this little assembler programm outputs "Hi" on UART_TX // // Put your code here: -//check tx status -(START) + +// Never +// 78 101 118 101 114 32 +@78 +D=A +@128 +M=D //N +@101 +D=A +@129 +M=D //e +@118 +D=A +@130 +M=D //v +@101 +D=A +@131 +M=D //e +@114 +D=A +@132 +M=D //r +@32 +D=A +@133 +M=D // space +// Graduate! +// 71 114 97 100 117 97 116 101 33 32 +@71 +D=A +@134 +M=D //G +@114 +D=A +@135 +M=D //r +@97 +D=A +@136 +M=D //a +@100 +D=A +@137 +M=D //d +@117 +D=A +@138 +M=D //u +@97 +D=A +@139 +M=D //a +@116 +D=A +@140 +M=D //t +@101 +D=A +@141 +M=D //e +@33 +D=A +@142 +M=D //! +@10 +D=A +@143 +M=D // newline +@128 +D=A +@CHARBOOT +M=D +@BOOT +0;JEQ + +(POLL) + @BUT + D=!M + @LED + M=D + @POLL + 0;JMP + +(WAITBOOT) @UART_TX D=M -@SENDH +@BOOT D;JEQ -@START +@WAITBOOT 0;JMP -(SENDH) -@72 -D=A -@UART_TX -M=D -(WAIT) -@UART_TX + +(BOOT) +@CHARBOOT +A=M D=M -@SENDI -D;JEQ -@WAIT -0;JMP -(SENDI) -@105 -D=A @UART_TX M=D -(END) -@END +@CHARBOOT +M=M+1 +@144 +D=A +@CHARBOOT +D=D-M +@ENDBOOT +D;JEQ +@WAITBOOT 0;JMP + +(ENDBOOT) +@POLL +0;JMP + + diff --git a/06_IO_Devices/02_UartRX/echo.asm b/06_IO_Devices/02_UartRX/echo.asm index 6f13196..770d415 100644 --- a/06_IO_Devices/02_UartRX/echo.asm +++ b/06_IO_Devices/02_UartRX/echo.asm @@ -4,3 +4,17 @@ // repeat in an endless loop // // Put your code here: +// hello.asm +// this little assembler programm outputs "Hi" on UART_TX +// +// Put your code here: + +(POLL) +@UART_RX +D=M +@UART_TX +M=D +@UART_RX +M=0 +@POLL +0;JMP diff --git a/06_IO_Devices/03_SPI/cat.asm b/06_IO_Devices/03_SPI/cat.asm index eb8747a..b9fa1c7 100644 --- a/06_IO_Devices/03_SPI/cat.asm +++ b/06_IO_Devices/03_SPI/cat.asm @@ -4,3 +4,159 @@ // data to UART_TX // // Put your code here: + +@171 +D=A +@SPI +M=D +@21 +D=A +@COUNT +M=D +(DECR) +@COUNT +DM=M-1 +@DECR +D;JGT +@3 +D=A +@SPI +M=D +(WAIT10) +@SPI +D=M +@WAIT10 +D;JLT +@4 +D=A +@SPI +M=D +(WAIT11) +@SPI +D=M +@WAIT11 +D;JLT +@SPI +M=0 +(WAIT12) +@SPI +D=M +@WAIT12 +D;JLT +@SPI +M=0 +(WAIT13) +@SPI +D=M +@WAIT13 +D;JLT +//(WAIT14) +//@SPI +//D=M +//@WAIT14 +//D;JLT +//@SPI +//D=M +//@128 +//M=D + +@4 +D=A +@SPI +M=D +(WAIT21) +@SPI +D=M +@WAIT21 +D;JLT +@SPI +M=0 +(WAIT22) +@SPI +D=M +@WAIT22 +D;JLT +@SPI +M=1 +(WAIT23) +@SPI +D=M +@WAIT23 +D;JLT +@SPI +D=M +@129 +M=D +@4 +D=A +@SPI +M=D +(WAIT31) +@SPI +D=M +@WAIT31 +D;JLT +@SPI +M=0 +(WAIT32) +@SPI +D=M +@WAIT32 +D;JLT +@2 +D=A +@SPI +M=D +(WAIT33) +@SPI +D=M +@WAIT33 +D;JLT +@SPI +D=M +@130 +M=D + start + @128 + D=A + @CHARBOOT + M=D + @BOOT + 0;JEQ + +(POLL) + @BUT + D=!M + @LED + M=D + @POLL + 0;JMP + +(WAITBOOT) + @UART_TX + D=M + @BOOT + D;JEQ + @WAITBOOT + 0;JMP + +(BOOT) + @CHARBOOT + A=M + D=M + @UART_TX + M=D + @CHARBOOT + M=M+1 + @131 + D=A + @CHARBOOT + D=D-M + @ENDBOOT + D;JEQ + @WAITBOOT + 0;JMP + +(ENDBOOT) + @POLL + 0;JMP diff --git a/06_IO_Devices/03_SPI/spi.txt b/06_IO_Devices/03_SPI/spi.txt new file mode 100644 index 0000000..dde425f --- /dev/null +++ b/06_IO_Devices/03_SPI/spi.txt @@ -0,0 +1 @@ +SPI! diff --git a/06_IO_Devices/GO.v b/06_IO_Devices/GO.v index f3ac9f2..2137994 100644 --- a/06_IO_Devices/GO.v +++ b/06_IO_Devices/GO.v @@ -22,5 +22,5 @@ module GO( end assign instruction = (active) ? sram_data : ROM_data; - assign SRAM_ADDR = (active) ? pc : sram_addr; + assign SRAM_ADDR = (active) ? sram_addr: pc; endmodule diff --git a/06_IO_Devices/HACK.v b/06_IO_Devices/HACK.v index 7591995..947419d 100644 --- a/06_IO_Devices/HACK.v +++ b/06_IO_Devices/HACK.v @@ -12,29 +12,29 @@ `default_nettype none module HACK( input CLK, // external clock 100 MHz - input [1:0] BUT, // user button ("pushed down" == 0) ("up" == 1) - output [1:0] LED, // leds (0 off, 1 on) - input UART_RX, // UART recieve - output UART_TX, // UART transmit - output SPI_SDO, // SPI data out - input SPI_SDI, // SPI data in - output SPI_SCK, // SPI serial clock - output SPI_CSX, // SPI chip select not - output [17:0] SRAM_ADDR,// SRAM address 18 Bit = 256K - inout [15:0] SRAM_DATA, // SRAM data 16 Bit - output SRAM_WEX, // SRAM write_enable_not - output SRAM_OEX, // SRAM output_enable_not - output SRAM_CSX, // SRAM chip_select_not - output LCD_DCX, // LCD data/command not - output LCD_SDO, // LCD data out - output LCD_SCK, // LCD serial clock - output LCD_CSX, // LCD chip select not - input RTP_SDI, // RTP data in s - output RTP_SDO, // RTP data out - output RTP_SCK // RTP serial clock + input [1:0] BUT, // user button ("pushed down" == 0) ("up" == 1) + output [1:0] LED, // leds (0 off, 1 on) + input UART_RX, // UART recieve + output UART_TX, // UART transmit + output SPI_SDO, // SPI data out + input SPI_SDI, // SPI data in + output SPI_SCK, // SPI serial clock + output SPI_CSX, // SPI chip select not + output [17:0] SRAM_ADDR,// SRAM address 18 Bit = 256K + inout [15:0] SRAM_DATA, // SRAM data 16 Bit + output SRAM_WEX, // SRAM write_enable_not + output SRAM_OEX, // SRAM output_enable_not + output SRAM_CSX, // SRAM chip_select_not + output LCD_DCX, // LCD data/command not + output LCD_SDO, // LCD data out + output LCD_SCK, // LCD serial clock + output LCD_CSX, // LCD chip select not + input RTP_SDI, // RTP data in s + output RTP_SDO, // RTP data out + output RTP_SCK // RTP serial clock ); - // Put your code here: + // Put your code here: wire loadRAM; wire loadIO0; wire loadIO1; @@ -57,18 +57,18 @@ module HACK( wire [15:0] inIO1; wire [15:0] inIO2; wire [15:0] inIO3; - wire [15:0] inIO4=0; - wire [15:0] inIO5=0; - wire [15:0] inIO6=0; - wire [15:0] inIO7=0; + wire [15:0] inIO4; + wire [15:0] inIO5; + wire [15:0] inIO6; + wire [15:0] inIO7; wire [15:0] inIO8=0; wire [15:0] inIO9=0; wire [15:0] inIOA=0; - wire [15:0] inIOB; - wire [15:0] inIOC; - wire [15:0] inIOD; - wire [15:0] inIOE; - wire [15:0] inIOF; + wire [15:0] inIOB=0; + wire [15:0] inIOC=0; + wire [15:0] inIOD=0; + wire [15:0] inIOE=0; + wire [15:0] inIOF=0; wire writeM; wire [15:0] inM; @@ -78,20 +78,26 @@ module HACK( wire [15:0] pc; wire clk, reset; - wire [15:0] outDEBUG0; - wire [15:0] outDEBUG1; - wire [15:0] outDEBUG2; - wire loadDEBUG0; - wire loadDEBUG1; - wire loadDEBUG2; + wire [15:0] ROM_DATA; + wire [15:0] fromLCD; + //wire [15:0] outDEBUG0; + //wire [15:0] outDEBUG1; + //wire [15:0] outDEBUG2; + //wire loadDEBUG0; + //wire loadDEBUG1; + //wire loadDEBUG2; // Put your code here: + //assign SRAM_ADDR[17:16]=2'b0; assign LED[1:0] = inIO0[1:0]; - assign outDEBUG0 = inIOB; - assign outDEBUG1 = inIOC; - assign outDEBUG2 = inIOD; - assign loadDEBUG0 = loadIOB; - assign loadDEBUG1 = loadIOC; - assign loadDEBUG2 = loadIOD; + assign inIO8 = fromLCD; + assign inIO9 = fromLCD; + + //assign outDEBUG0 = inIOB; + //assign outDEBUG1 = inIOC; + //assign outDEBUG2 = inIOD; + //assign loadDEBUG0 = loadIOB; + //assign loadDEBUG1 = loadIOC; + //assign loadDEBUG2 = loadIOD; Clock25_Reset20 CLKR(CLK, clk, reset); CPU CPU(clk, inM, instruction, reset, outM, writeM, addressM, pc); @@ -110,19 +116,22 @@ module HACK( UartTX UartTX(clk, loadIO2, outM, UART_TX, inIO2); UartRX UartRX(clk, loadIO3, UART_RX, inIO3); - //SPI SPI(clk, loadIO4, outM, inIO4, SPI_CSX, SPI_SDO, SPI_SDI, SPI_SCK); - //GO GO(clk, loadIO5, pc, sram_addr, SRAM_ADDR, sram_data, ROM_data, instruction); + SPI SPI(clk, loadIO4, outM, inIO4, SPI_CSX, SPI_SDO, SPI_SDI, SPI_SCK); + //GO GO(clk, loadIO5, pc, inIO6, SRAM_ADDR[15:0], inIO7, ROM_DATA, instruction); + //Register SRAM_A(clk, outM, loadIO0, inIO6); + //SRAM_D SRAM_D(clk, loadIO7, outM, inIO7, SRAM_DATA, SRAM_CSX, SRAM_OEX, SRAM_WEX); + //LCD LCD(clk, loadIO8, loadIO9, outM, fromLCD, LCD_DCX, LCD_CSX, LCD_SDO, LCD_SCK); - Register DEBUG0(clk, outM, loadIOB, inIOB); - Register DEBUG1(clk, outM, loadIOC, inIOC); - Register DEBUG2(clk, outM, loadIOD, inIOD); - Register DEBUG3(clk, outM, loadIOE, inIOE); - Register DEBUG4(clk, outM, loadIOF, inIOF); + //Register DEBUG0(clk, outM, loadIOB, inIOB); + //Register DEBUG1(clk, outM, loadIOC, inIOC); + //Register DEBUG2(clk, outM, loadIOD, inIOD); + //Register DEBUG3(clk, outM, loadIOE, inIOE); + //Register DEBUG4(clk, outM, loadIOF, inIOF); + +//assign SPI_SDO=0; +//assign SPI_SCK=0; +//assign SPI_CSX=0; -assign SPI_SDO=0; -assign SPI_SCK=0; -assign SPI_CSX=0; -assign SRAM_ADDR=0; assign SRAM_DATA=0; assign SRAM_WEX=0; assign SRAM_OEX=0; @@ -134,3 +143,4 @@ assign LCD_CSX=0; assign RTP_SDO=0; assign RTP_SCK=0; endmodule + diff --git a/06_IO_Devices/LCD.v b/06_IO_Devices/LCD.v index d0554d1..cacda69 100644 --- a/06_IO_Devices/LCD.v +++ b/06_IO_Devices/LCD.v @@ -16,17 +16,105 @@ */ `default_nettype none module LCD( - input clk, //clock 25 MHz - input load, //start send command/byte over SPI - input load16, //start send data (16 bits) - input [15:0] in, //data to be send - output [15:0] out, //data to be send - output DCX, //SPI data/command not - output CSX, //SPI chip select not - output SDO, //SPI serial data out - output SCK //SPI serial clock + input clk, //clock 25 MHz + input load, //start send command/byte over SPI + input load16, //start send data (16 bits) + input [15:0] in, //data to be send + output reg [15:0] out, //data to be send + output reg DCX, //SPI data/command not + output reg CSX, //SPI chip select not + output reg SDO, //SPI serial data out + output reg SCK //SPI serial clock ); - // Put your code here: + // Put your code here: + reg [15:0] to_send; + reg [3:0] nthbit=0; + reg csx_low=0; + reg is_data=0; + reg active=0; + reg active16=0; + reg [4:0] is16; + always @(posedge clk) begin + SDO <= 0; + SCK <= 0; + CSX <= (csx_low) ? 0 : 1; + DCX <= (is_data) ? 1 : 0; + out <= (load || load16 || active || active16) ? 16'h8000 : 16'h0000; + + if (load && ~active && ~active16) begin + if (in[8]) begin + csx_low <= 0; + CSX <= 1; + end else begin + active <= 1; + is16 <= 1; + csx_low <= 1; + CSX <= 0; + is_data <= in[9]; + DCX <= in[9]; + to_send <= in; + SDO <= in[7]; + end + end + else if (load16 && ~active && ~active16) begin + active16 <= 1; + is16 <= 1; + csx_low <= 1; + to_send <= in; + SDO <= in[15]; + end + else if (active) begin + SCK <= ~SCK; + if ( is16 == 15) begin + active <= 0; + SDO <= to_send[0]; + end + else begin + is16 <= is16 + 1; + SDO <= SDO; + case (is16) + 2 : SDO <= to_send[6]; + 4 : SDO <= to_send[5]; + 6 : SDO <= to_send[4]; + 8 : SDO <= to_send[3]; + 10 : SDO <= to_send[2]; + 12 : SDO <= to_send[1]; + 14 : SDO <= to_send[0]; + endcase + + end + end + else if (active16) begin + SCK <= ~SCK; + if ( is16 == 31) begin + active16 <= 0; + SDO <= to_send[0]; + end + else begin + is16 <= is16 + 1; + SDO <= SDO; + case (is16) + 2 : SDO <= to_send[14]; + 4 : SDO <= to_send[13]; + 6 : SDO <= to_send[12]; + 8 : SDO <= to_send[11]; + 10 : SDO <= to_send[10]; + 12 : SDO <= to_send[9]; + 14 : SDO <= to_send[8]; + 16 : SDO <= to_send[7]; + 18 : SDO <= to_send[6]; + 20 : SDO <= to_send[5]; + 22 : SDO <= to_send[4]; + 24 : SDO <= to_send[3]; + 26 : SDO <= to_send[2]; + 28 : SDO <= to_send[1]; + 30 : SDO <= to_send[0]; + endcase + + end + end + end + endmodule diff --git a/06_IO_Devices/SPI.v b/06_IO_Devices/SPI.v index 76b0ca5..a715abb 100644 --- a/06_IO_Devices/SPI.v +++ b/06_IO_Devices/SPI.v @@ -22,76 +22,74 @@ module SPI( // Put your code here: // 1100 0000 0101 1011 // 1000 0000 0101 1011 - reg temp; reg active=0; + reg csx_low=0; + reg out_low=1; reg [7:0] totx; reg [7:0] torx; - reg [11:0] is216; + reg [4:0] is16; always @(posedge clk) begin - CSX <= 0; + CSX <= (csx_low) ? 0 : 1; SDO <= 0; SCK <= 0; out <= (out)? out : 0; if (load == 1) begin + out_low=0; out[14:8] <= 0; out[7:0] <= in[7:0]; if (in[8]==1) begin out[15] <= 0; + csx_low <= 0; CSX <= 1; end else if (in[8]==0) begin out[15] <= 1; + csx_low <= 1; CSX <= 0; active <= 1; - is216 <= 1; + is16 <= 1; totx[7:0] <= in[7:0]; SDO <= in[7]; - //out <= (out<<1); - //out[0] <= SDI; - //torx[7] <= SDI; end end else if (active==1) begin SCK <= ~SCK; - if (is216 == 16) begin + if (is16 == 16) begin active <= 0; - CSX <= CSX; out <= {8'b0, torx[7:0]}; end else begin - CSX <= 0; - is216 <= is216 + 1; - //SDO <= totx[7-(is216/2)]; - torx[7-(is216/2)] <= SDI; - case (is216+1) - 2 : SDO <= totx[7]; - 3 : SDO <= totx[6]; - 4 : SDO <= totx[6]; - 5 : SDO <= totx[5]; - 6 : SDO <= totx[5]; - 7 : SDO <= totx[4]; - 8 : SDO <= totx[4]; - 9 : SDO <= totx[3]; - 10 : SDO <= totx[3]; - 11 : SDO <= totx[2]; - 12 : SDO <= totx[2]; - 13 : SDO <= totx[1]; - 14 : SDO <= totx[1]; - 15 : SDO <= totx[0]; - 16 : SDO <= totx[0]; - endcase - - // case (is216) - // 3 : torx[6] <= SDI; - // 5 : torx[5] <= SDI; - // 7 : torx[4] <= SDI; - // 9 : torx[3] <= SDI; - // 11 : torx[2] <= SDI; - // 13 : torx[1] <= SDI; - // 15 : torx[0] <= SDI; - // endcase - case (is216) + csx_low <= 1; + is16 <= is16 + 1; + case (is16+1) + 2 : SDO <= totx[7]; + 3 : SDO <= totx[6]; + 4 : SDO <= totx[6]; + 5 : SDO <= totx[5]; + 6 : SDO <= totx[5]; + 7 : SDO <= totx[4]; + 8 : SDO <= totx[4]; + 9 : SDO <= totx[3]; + 10 : SDO <= totx[3]; + 11 : SDO <= totx[2]; + 12 : SDO <= totx[2]; + 13 : SDO <= totx[1]; + 14 : SDO <= totx[1]; + 15 : SDO <= totx[0]; + 16 : SDO <= totx[0]; + endcase + case (is16) + 1 : torx[7] <= SDI; + 3 : torx[6] <= SDI; + 5 : torx[5] <= SDI; + 7 : torx[4] <= SDI; + 9 : torx[3] <= SDI; + 11 : torx[2] <= SDI; + 13 : torx[1] <= SDI; + 15 : torx[0] <= SDI; + endcase + case (is16) 2 : out <= (out<<1); 4 : out <= (out<<1); 6 : out <= (out<<1); @@ -100,7 +98,7 @@ module SPI( 12 : out <= (out<<1); 14 : out <= (out<<1); endcase - case (is216) + case (is16) 2 : out[0] <= torx[7]; 4 : out[0] <= torx[6]; 6 : out[0] <= torx[5]; @@ -109,19 +107,18 @@ module SPI( 12 : out[0] <= torx[2]; 14 : out[0] <= torx[1]; endcase - case (is216) - 2 : out[15:8] <= {8'b10000000}; - 4 : out[15:8] <= {8'b10000000}; - 6 : out[15:8] <= {8'b10000000}; - 8 : out[15:8] <= {8'b10000000}; - 10 : out[15:8] <= {8'b10000000}; - 12 : out[15:8] <= {8'b10000000}; - 14 : out[15:8] <= {8'b10000000}; + case (is16) + 2 : out[15:8] <= 8'b10000000; + 4 : out[15:8] <= 8'b10000000; + 6 : out[15:8] <= 8'b10000000; + 8 : out[15:8] <= 8'b10000000; + 10 : out[15:8] <= 8'b10000000; + 12 : out[15:8] <= 8'b10000000; + 14 : out[15:8] <= 8'b10000000; endcase end end else begin - CSX <= CSX; - out <= out? out : 16'b0; + out <= out_low? 16'b0 : out; end end endmodule diff --git a/06_IO_Devices/SRAM_D.v b/06_IO_Devices/SRAM_D.v index fef2fc5..686e11a 100644 --- a/06_IO_Devices/SRAM_D.v +++ b/06_IO_Devices/SRAM_D.v @@ -16,27 +16,32 @@ module SRAM_D( output [15:0] out, inout [15:0] DATA, // SRAM data 16 Bit output CSX, // SRAM chip_enable_not - output reg OEX, // SRAM output_enable_not - output reg WEX // SRAM write_enable_not + output OEX, // SRAM output_enable_not + output WEX // SRAM write_enable_not ); // Put your code here: - reg [15:0] to_sram; - always @(posedge clk) begin - if (load) begin - OEX <= 1; - WEX <= 0; - to_sram <= in; - end else begin - OEX <= 0; - WEX <= 1; - end - end - //DFF DFF(clk, load, LOAD); - //Register Register(clk, in, load, to_sram); - // assign OEX = (LOAD) ? 1 : 0; - // assign WEX = (LOAD) ? 0 : 1; + wire LOAD; + wire [15:0] to_sram; + // always @(posedge clk) begin + // if (load) begin + // OEX <= 1; + // WEX <= 0; + // //to_sram <= in; + // end else begin + // OEX <= 0; + // WEX <= 1; + // end + // end assign CSX = 0; + assign OEX = (LOAD) ? 1 : 0; + assign WEX = (LOAD) ? 0 : 1; + + DFF DFF(clk, load, LOAD); + Register Register(clk, in, load, to_sram); + //if (dir == 0) IN: PIN are set to High-Z, dataR = external PIN + //if (dir == 1) OUTPUT: dataW is output to external PIN, dataR = dataW + InOut InOut(DATA, to_sram, out, OEX); endmodule diff --git a/06_IO_Devices/UartRX.v b/06_IO_Devices/UartRX.v index caf3469..9aa04d8 100644 --- a/06_IO_Devices/UartRX.v +++ b/06_IO_Devices/UartRX.v @@ -17,13 +17,15 @@ module UartRX( // Put your code here: wire clkdRX; reg active=0; + reg out_set=0; reg [7:0] uart; reg [3:0] nthbit; - reg [11:0] is216; + reg [9:0] is216; always @(posedge clk) begin - out <= clear ? 16'h8000 : out; - + out_set <= clear ? 1 : out_set; + out <= clear ? 16'h8000 : (out_set ? out : 16'h0000); if ((active==0) && (RX == 0)) begin + out_set <=1; active <= 1; is216 <= 1; uart <= 0; diff --git a/06_IO_Devices/UartTX.v b/06_IO_Devices/UartTX.v index 6d3f5e6..37592e9 100644 --- a/06_IO_Devices/UartTX.v +++ b/06_IO_Devices/UartTX.v @@ -20,7 +20,7 @@ module UartTX( reg active=0; reg [7:0] to_send; reg [3:0] nthbit=0; - reg [11:0] is216; + reg [9:0] is216; always @(posedge clk) begin out <= (load || active) ? 16'h8000 : 16'h0000;