build hack with UART TX / RX support

06_IO_Devices/01_UartTX/hello.asm

@@ -2,3 +2,31 @@
 // this little assembler programm outputs "Hi" on UART_TX
 // 
 // Put your code here:
+//check tx status
+(START)
+@UART_TX
+D=M
+@SENDH
+D;JEQ
+@START
+0;JMP
+(SENDH)
+@72
+D=A
+@UART_TX
+M=D
+(WAIT)
+@UART_TX 
+D=M
+@SENDI
+D;JEQ
+@WAIT
+0;JMP
+(SENDI)
+@105
+D=A
+@UART_TX
+M=D
+(END)
+@END
+0;JMP

06_IO_Devices/HACK.v

@@ -35,5 +35,102 @@ module HACK(
 );
 
 	// Put your code here:
+    wire loadRAM;
+    wire loadIO0;
+    wire loadIO1;
+    wire loadIO2;
+    wire loadIO3;
+    wire loadIO4;
+    wire loadIO5;
+    wire loadIO6;
+    wire loadIO7;
+    wire loadIO8;
+    wire loadIO9;
+    wire loadIOA;
+    wire loadIOB;
+    wire loadIOC;
+    wire loadIOD;
+    wire loadIOE;
+    wire loadIOF;
+    wire [15:0] inRAM;
+    wire [15:0] inIO0;
+    wire [15:0] inIO1;
+    wire [15:0] inIO2;
+    wire [15:0] inIO3;
+    wire [15:0] inIO4=0;
+    wire [15:0] inIO5=0;
+    wire [15:0] inIO6=0;
+    wire [15:0] inIO7=0;
+    wire [15:0] inIO8=0;
+    wire [15:0] inIO9=0;
+    wire [15:0] inIOA=0;
+    wire [15:0] inIOB;
+    wire [15:0] inIOC;
+    wire [15:0] inIOD;
+    wire [15:0] inIOE;
+    wire [15:0] inIOF;
 
+    wire writeM;
+    wire [15:0] inM;
+    wire [15:0] instruction;
+    wire [15:0] outM;
+    wire [15:0] addressM;
+    wire [15:0] pc;
+
+    wire clk, reset;
+    wire [15:0] outDEBUG0;
+    wire [15:0] outDEBUG1;
+    wire [15:0] outDEBUG2;
+    wire loadDEBUG0;
+    wire loadDEBUG1;
+    wire loadDEBUG2;
+    // Put your code here:
+    assign LED[1:0] = inIO0[1:0];
+    assign outDEBUG0 = inIOB;
+    assign outDEBUG1 = inIOC;
+    assign outDEBUG2 = inIOD;
+    assign loadDEBUG0 = loadIOB;
+    assign loadDEBUG1 = loadIOC;
+    assign loadDEBUG2 = loadIOD;
+    Clock25_Reset20 CLKR(CLK, clk, reset);
+    CPU CPU(clk, inM, instruction, reset, outM, writeM, addressM, pc);
+
+    Memory Memory(addressM, writeM, inM, loadRAM,
+        loadIO0, loadIO1, loadIO2, loadIO3, loadIO4, loadIO5, loadIO6, loadIO7,
+        loadIO8, loadIO9, loadIOA, loadIOB, loadIOC, loadIOD, loadIOE, loadIOF,
+        inRAM, inIO0, inIO1, inIO2, inIO3, inIO4, inIO5, inIO6, inIO7,
+        inIO8, inIO9, inIOA, inIOB, inIOC, inIOD, inIOE, inIOF);
+
+    ROM ROM(pc, instruction);
+    RAM3840 RAM(clk, addressM[11:0], outM, loadRAM, inRAM);
+
+    Register LED12(clk, outM, loadIO0, inIO0);
+    Register BUT12(clk, {14'b0, BUT[1:0]}, 1'b1, inIO1);
+
+    UartTX UartTX(clk, loadIO2, outM, UART_TX, inIO2);
+    UartRX UartRX(clk, loadIO3, UART_RX, inIO3);
+
+    //SPI SPI(clk, loadIO4, outM, inIO4, SPI_CSX, SPI_SDO, SPI_SDI, SPI_SCK);
+    //GO GO(clk, loadIO5, pc, sram_addr, SRAM_ADDR, sram_data, ROM_data, instruction);
+
+    Register DEBUG0(clk, outM, loadIOB, inIOB);
+    Register DEBUG1(clk, outM, loadIOC, inIOC);
+    Register DEBUG2(clk, outM, loadIOD, inIOD);
+    Register DEBUG3(clk, outM, loadIOE, inIOE);
+    Register DEBUG4(clk, outM, loadIOF, inIOF);
+
+assign SPI_SDO=0;
+assign SPI_SCK=0;
+assign SPI_CSX=0;
+assign SRAM_ADDR=0;
+assign SRAM_DATA=0;
+assign SRAM_WEX=0;
+assign SRAM_OEX=0;
+assign SRAM_CSX=0;
+assign LCD_DCX=0;
+assign LCD_SDO=0;
+assign LCD_SCK=0;
+assign LCD_CSX=0;
+assign RTP_SDO=0;
+assign RTP_SCK=0;
 endmodule

06_IO_Devices/UartRX.v

@@ -7,7 +7,6 @@
  * of byte completes, chip ouputs the received byte to out[7:0]] with out[15]=0.
  */
 `default_nettype none
-
 module UartRX(
     input clk,
     input clear,
@@ -18,8 +17,8 @@ module UartRX(
     // Put your code here:
     wire clkdRX;
     reg active=0;
-    reg [8:0] uart;
+    reg [7:0] uart;
-    reg [11:0] is108;
+    reg [3:0] nthbit;
     reg [11:0] is216;
     always @(posedge clk) begin
         out <= clear ? 16'h8000 : out;
@@ -28,28 +27,25 @@ module UartRX(
             active <= 1;
             is216 <= 1;
             uart <= 0;
+            nthbit <= 0;
         end
         else if (active==1) begin
-            if (is216 == 2169) begin
+            is216 <= (is216 == 216) ? 0 : is216 + 1;
+            nthbit <= (is216 == 108) ? nthbit + 1 : nthbit;
+            case (nthbit)
+                1 : uart[0] <= RX;
+                2 : uart[1] <= RX;
+                3 : uart[2] <= RX;
+                4 : uart[3] <= RX;
+                5 : uart[4] <= RX;
+                6 : uart[5] <= RX;
+                7 : uart[6] <= RX;
+                8 : uart[7] <= RX;
+            endcase
+            if (nthbit == 10 && is216 == 216) begin
                 active <= 0;
                 out <= {8'b0, uart};
             end
-            else begin
-                is216 <= is216 + 1;
-                is108 <= is216 / 108;
-                case (is108)
-                    3  : uart[0] <= clkdRX;
-                    5  : uart[1] <= clkdRX;
-                    7  : uart[2] <= clkdRX;
-                    9  : uart[3] <= clkdRX;
-                    11 : uart[4] <= clkdRX;
-                    13 : uart[5] <= clkdRX;
-                    15 : uart[6] <= clkdRX;
-                    17 : uart[7] <= clkdRX;
-                endcase
         end
     end
-    end
-
-    DFF DFF(clk, RX, clkdRX);
 endmodule

06_IO_Devices/UartTX.v

@@ -16,9 +16,9 @@ module UartTX(
     output reg [15:0] out
 );
 
-    // Put your code here:
     reg uart=1;
     reg active=0;
+    reg [7:0] to_send;
     reg [3:0] nthbit=0;
     reg [11:0] is216;
     always @(posedge clk) begin
@@ -27,31 +27,28 @@ module UartTX(
         if ((active==0) && (load == 1)) begin
             active <= 1;
             is216  <= 1;
+            nthbit <= 0;
             uart   <= 0;
+            to_send <= in[7:0];
         end
         else if (active==1) begin
-            if (is216 == 2170) begin
+            is216 <= (is216 == 216) ? 0 : is216 + 1;
-                active <= 0;
+            nthbit <= (is216 == 216) ? nthbit + 1 : nthbit;
-                out <= 16'h0000;
-            end
-            else begin
-                is216 <= is216 + 1;
-                nthbit <= (is216 + 1) / 217;
             case (nthbit)
                 0 : uart <= 0;
-                    1 : uart <= in[nthbit-1];
+                1 : uart <= to_send[0];
-                    2 : uart <= in[nthbit-1];
+                2 : uart <= to_send[1];
-                    3 : uart <= in[nthbit-1];
+                3 : uart <= to_send[2];
-                    4 : uart <= in[nthbit-1];
+                4 : uart <= to_send[3];
-                    5 : uart <= in[nthbit-1];
+                5 : uart <= to_send[4];
-                    6 : uart <= in[nthbit-1];
+                6 : uart <= to_send[5];
-                    7 : uart <= in[nthbit-1];
+                7 : uart <= to_send[6];
-                    8 : uart <= in[nthbit-1];
+                8 : uart <= to_send[7];
                 9 : uart <= 1;
+                10 : begin active <= 0; out <= 16'h0000; end
             endcase
         end
     end
-    end
     assign TX = uart;
 
 endmodule