25 lines
480 B
Coq
25 lines
480 B
Coq
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/**
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* RAM implements 3840 Bytes of RAM addressed from 0000 - 3839
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* out = M[address]
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* if (load =i= 1) M[address][t+1] = in[t]
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*/
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`default_nettype none
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module RAM3840(
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input clk,
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input [15:0] address,
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input [15:0] in,
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input load,
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output [15:0] out
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);
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// No need to implement this chip
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// RAM is implemented using BRAM of iCE40
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reg [15:0] regRAM [0:3839];
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always @(posedge clk)
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if (load) regRAM[address[11:0]] <= in;
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assign out = regRAM[address[11:0]];
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endmodule
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