61 lines
1017 B
Coq
61 lines
1017 B
Coq
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`default_nettype none
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module RAM512_tb();
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// IN,OUT
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reg clk=1;
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reg [15:0] in;
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reg [8:0] address;
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reg load;
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wire [15:0] out;
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// Part
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RAM512 RAM512(
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.clk(clk),
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.address(address),
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.in(in),
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.load(load),
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.out(out)
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);
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// Simulate
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always #1 clk=~clk;
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always @(posedge clk) begin
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in <= $random;
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address <= n;
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load <= (n<512);
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end
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// Compare
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reg [15:0] regRAM [0:511];
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always @(posedge clk)
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if (load) regRAM[address[8:0]] <= in;
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wire[15:0] out_cmp = regRAM[address[8:0]];
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reg fail = 0;
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reg [15:0] n = 0;
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task check;
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#1
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if (out != out_cmp)
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begin
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$display("FAIL: clk=%1b, address=%9b, in=%16b, load=%1b, out=%16b",clk,address,in,load,out);
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fail=1;
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end
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endtask
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initial begin
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$dumpfile("RAM512_tb.vcd");
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$dumpvars(0, RAM512_tb);
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$display("------------------------");
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$display("Testbench: RAM512");
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for (n=0; n<1000;n=n+1)
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check();
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if (fail==0) $display("passed");
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$display("------------------------");
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$finish;
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end
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endmodule
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