nand2/06_IO_Devices/UartTX.v

/**
 * UartTX controls transmission of bytes over UART.
 *
 * When load = 1 the chip starts serial transmission of the byte in[7:0] to the
 * TX line according to the protocoll 8N1 with 115200 baud. During transmission
 * out[15] is set to high (busy). The transmission is finished after 2170 clock 
 * cycles (10 byte a 217 cycle each). When transmission completes out[15] goes
 * low again (ready). 
 */
`default_nettype none
module UartTX(
    input clk,
    input load,
    input [15:0] in,
    output TX,
    output reg [15:0] out
);

    // Put your code here:
    reg uart=1;
    reg active=0;
    reg [3:0] nthbit=0;
    reg [11:0] is216;
    always @(posedge clk) begin
        out <= (load || active) ? 16'h8000 : 16'h0000;

        if ((active==0) && (load == 1)) begin
            active <= 1;
            is216 <= 1;
            uart <= 0;
        end
        else if (active==1) begin
            if (is216 == 2170) begin
                active <= 0;
                out <= 16'h0000;
            end
            else begin
                is216 <= is216 + 1;
                nthbit <= (is216 + 1) / 217;
                case (nthbit)
                    0 : uart <= 0;
                    1 : uart <= in[nthbit-1];
                    2 : uart <= in[nthbit-1];
                    3 : uart <= in[nthbit-1];
                    4 : uart <= in[nthbit-1];
                    5 : uart <= in[nthbit-1];
                    6 : uart <= in[nthbit-1];
                    7 : uart <= in[nthbit-1];
                    8 : uart <= in[nthbit-1];
                    9 : uart <= 1;
                endcase
            end
        end
    end
    assign TX = uart;

endmodule