61 lines
1.0 KiB
Coq
61 lines
1.0 KiB
Coq
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`timescale 10ns/1ns
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`default_nettype none
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module HACK_tb();
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reg CLK = 0;
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reg [1:0] BUT = 3;
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wire [1:0] LED;
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wire RX,TX;
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wire LCD_DCX,LCD_SDO,LCD_SCK,LCD_CSX;
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wire RTP_SDI;
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wire RTP_SCK,RTP_SDO;
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HACK HACK(
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.CLK(CLK),
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.BUT(BUT),
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.LED(LED),
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.UART_RX(RX),
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.UART_TX(TX),
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.LCD_DCX(LCD_DCX),
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.LCD_SDO(LCD_SDO),
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.LCD_SCK(LCD_SCK),
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.LCD_CSX(LCD_CSX),
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.RTP_SDO(RTP_SDO),
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.RTP_SDI(RTP_SDI),
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.RTP_SCK(RTP_SCK)
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);
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always #0.5 CLK = ~CLK;
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//Simulate UART
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reg [9:0] uart = 10'b1111111111;
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reg [15:0] baudrate = 0;
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always @(posedge CLK)
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baudrate <= (baudrate==866)?0:baudrate+1;
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always @(posedge CLK)
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if (baudrate==0) uart <= {1'b1,uart[9:1]};
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assign RX = uart[0];
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//Simulate RTP
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reg [40:0] spi={1'b0,8'd128,8'd10,8'd25,8'd8,8'd22};
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assign RTP_SDI = spi[40];
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always @(posedge (RTP_SCK))
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spi <= {spi[39:0],1'b0};
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initial begin
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$dumpfile("HACK_tb.vcd");
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$dumpvars(0, HACK_tb);
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#15000
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#30000
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#30000 uart = (("R"<<2)|1);
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#30000 uart = (("X"<<2)|1);
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#30000
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#30000 BUT = 1;
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#30000
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#30000 BUT = 0;
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#400000
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$finish;
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end
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endmodule
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