23 lines
444 B
Coq
23 lines
444 B
Coq
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/**
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* 8-bit Shiftregister (shifts to left)
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* if (load == 1) out[t+1] = in[t]
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* else if (shift == 1) out[t+1] = out[t]<<1 | inLSB
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* (shift one position to left and insert inLSB as least significant bit)
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*/
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`default_nettype none
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module BitShift8L(
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input clk,
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input [7:0] in,
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input inLSB,
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input load,
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input shift,
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output [7:0] out
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);
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reg [7:0] out=0;
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always @(posedge clk)
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out <= load?in:(shift?{out[6:0],inLSB}:out);
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endmodule
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