122 lines
3.1 KiB
Coq
122 lines
3.1 KiB
Coq
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`timescale 10ns/1ns
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`default_nettype none
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module HACK_tb();
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// IN,OUT
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reg CLK = 1;
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reg [1:0] BUT = 3;
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wire [1:0] LED;
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wire UART_TX;
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wire UART_RX;
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wire SPI_SDO;
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wire SPI_SDI;
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wire SPI_SCK;
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wire SPI_CSX;
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wire [17:0] SRAM_ADDR;
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wire [15:0] SRAM_DATA;
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wire SRAM_WEX;
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wire SRAM_OEX;
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wire SRAM_CSX;
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wire LCD_DCX;
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wire LCD_SDO;
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wire LCD_SCK;
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wire LCD_CSX;
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reg RTP_SDI;
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wire RTP_SDO;
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wire RTP_SCK;
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// Part
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HACK HACK(
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.CLK(CLK), // external clock 100 MHz
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.BUT(BUT), // user button ("pushed down" == 0) ("up" == 1)
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.LED(LED), // leds (0 off, 1 on)
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.UART_RX(UART_RX), // UART receive
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.UART_TX(UART_TX), // UART transmit
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.SPI_SDO(SPI_SDO), // SPI serial data out
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.SPI_SDI(SPI_SDI), // SPI serial data in
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.SPI_SCK(SPI_SCK), // SPI serial clock
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.SPI_CSX(SPI_CSX), // SPI chip select not
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.SRAM_ADDR(SRAM_ADDR), // SRAM address 18 Bit = 256K
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.SRAM_DATA(SRAM_DATA), // SRAM data 16 Bit
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.SRAM_WEX(SRAM_WEX), // SRAM write_enable_not
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.SRAM_OEX(SRAM_OEX), // SRAM output_enable_not
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.SRAM_CSX(SRAM_CSX), // SRAM chip_select_not
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.LCD_DCX(LCD_DCX), // LCD data/command not
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.LCD_SDO(LCD_SDO), // LCD serial data out
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.LCD_SCK(LCD_SCK), // LCD serial clock
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.LCD_CSX(LCD_CSX), // LCD chip select not
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.RTP_SDI(RTP_SDI), // RTP serial data in
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.RTP_SDO(RTP_SDO), // RTP serial data out in
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.RTP_SCK(RTP_SCK) // RTP serial clock
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);
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// Simulate
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always #0.5 CLK = ~CLK;
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integer n=0;
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always @(posedge CLK) n=n+1;
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// Compare
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reg [9:0] uart=10'b1111111111;
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reg [15:0] baudrate = 0;
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always @(posedge CLK)
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baudrate <= ((baudrate==866)?0:baudrate+1);
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always @(posedge CLK) begin
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uart <= (n==5000)?((82<<2)+1):(n==15000)?((88<<2)+1):((baudrate==866)?{1'b1,uart[9:1]}:uart);
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end
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wire shift = (baudrate==866);
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assign UART_RX = uart[0];
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//Simulate SPI
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reg spi_sleep=1;
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reg [31:0] spi_cmd=0;
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reg [95:0] spi=0;
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assign SPI_SDI = (SPI_CSX | spi_sleep) ? 1'bz:spi[95];
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always @(posedge (SPI_SCK))
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spi <= {spi[95:0],1'b0};
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always @(posedge (SPI_SCK))
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spi_cmd <= {spi_cmd[30:0],SPI_SDO};
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always @(negedge (SPI_CSX))
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spi_cmd <= 0;
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always @(spi_cmd) begin
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if (spi_cmd==32'h000000AB) spi_sleep <= 0;
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if (spi_cmd==32'h000000B9) spi_sleep <= 1;
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if (spi_cmd==32'h03040000) spi <= "SPI! 123";
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if (spi_cmd==32'h03010000) spi <= 96'h1001_FC10_1000_E308_0000_EA87;
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end
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//Simulate SRAM
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reg [16:0] sram[0:7];
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always @(posedge CLK)
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if (~SRAM_WEX&&SRAM_OEX&&~SRAM_CSX) sram[SRAM_ADDR] <= SRAM_DATA;
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assign SRAM_DATA = (~SRAM_CSX&&~SRAM_OEX)?sram[SRAM_ADDR]:16'bzzzzzzzzzzzzzzzz;
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//Simulate LCD
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reg [7:0] lcd_c;
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reg [15:0] lcd_d;
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always @(posedge LCD_SCK) begin
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lcd_c <= (~LCD_DCX)?{lcd_c[6:0],LCD_SDO}:lcd_c;
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lcd_d <= (LCD_DCX)?{lcd_d[6:0],LCD_SDO}:lcd_d;
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end
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always @(negedge LCD_CSX) begin
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lcd_c <= 0;
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lcd_d <= 0;
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end
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//simulate BUT
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always @(posedge CLK) begin
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if (n==10000) BUT<=0;
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if (n==20000) BUT<=1;
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if (n==30000) BUT<=2;
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end
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initial begin
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$dumpfile("HACK_tb.vcd");
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$dumpvars(0, HACK_tb);
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$display("------------------------");
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$display("Testbench: Hack");
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#40000
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$finish;
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end
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endmodule
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