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/**
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2024-10-17 18:36:58 +00:00
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* Nand gate:
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* out = 0 if (a == 1 and b == 1)
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* 1 otherwise
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*/
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`default_nettype none
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module Nand(
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input a,
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input b,
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output out
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);
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2024-10-17 18:36:58 +00:00
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// No need to implement this chip
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// This chip is implemented using verilog primitives
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nand(out,a,b);
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endmodule
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