87 lines
2.1 KiB
Coq
87 lines
2.1 KiB
Coq
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`default_nettype none
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module CPU_tb();
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// IN,OUT
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reg clk=1;
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reg [15:0] inM=0;
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reg [15:0] instruction=0;
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reg reset=1;
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wire [15:0] outM;
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wire writeM;
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wire [15:0] addressM;
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wire [15:0] pc;
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// Part
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CPU CPU(
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.clk(clk),
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.inM(inM),
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.instruction(instruction),
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.reset(reset),
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.outM(outM),
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.writeM(writeM),
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.addressM(addressM),
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.pc(pc)
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);
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// Simulation
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always #1 clk=~clk;
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always @(posedge clk) begin
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inM <= $random;
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reset <= (n<=10) || ((n>20) && (n<40));
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instruction <= $random;
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end
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// Compare
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reg [15:0] addressM_cmp=0;
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reg [15:0] regD=0;
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reg [15:0] pc_cmp=0;
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reg zx,nx,zy,ny,f,no;
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wire [15:0] out_cmp;
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wire [15:0] x,y;
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wire zr,ng;
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assign x = instruction[10]?(instruction[11]?~0:~regD):(instruction[11]?0:regD);
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assign y = instruction[8]?(instruction[9]?~0:~(instruction[12]?inM:addressM_cmp)):(instruction[9]?0:(instruction[12]?inM:addressM_cmp));
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assign out_cmp = instruction[6]?(instruction[7]?~(x+y):~(x&y)):(instruction[7]?(x+y):(x&y));
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wire comp;
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wire jmp;
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assign comp = instruction[15] && instruction[14] && instruction[13];
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assign zr = (out_cmp==0);
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assign ng = out_cmp[15];
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assign jmp = comp && ((ng&&instruction[2])||(zr&&instruction[1])||(~(ng|zr)&&instruction[0]));
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always @(posedge clk) begin
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addressM_cmp <= comp?(instruction[5]?out_cmp:addressM_cmp) : instruction;
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regD <= comp?(instruction[4]?out_cmp:regD) : regD;
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pc_cmp <= reset?0 : (jmp?addressM_cmp:pc_cmp+1);
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end
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wire writeM_cmp;
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assign writeM_cmp = comp?instruction[3]:0;
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reg fail = 0;
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reg [15:0] n = 0;
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task check;
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#1
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if ((pc != pc_cmp) || (addressM != addressM_cmp) || (outM != out_cmp) || (writeM != writeM_cmp))
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begin
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$display("FAIL: clk=%1b, inM=%16b, instruction=%16b, reset=%1b, outM=%16b, writeM=%1b, addressM=%16b, pc=%16b",clk,inM,instruction,reset,outM,writeM,addressM,pc);
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fail=1;
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end
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endtask
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// Test
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initial begin
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$dumpfile("CPU_tb.vcd");
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$dumpvars(0, CPU_tb);
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$display("------------------------");
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$display("Testbench: CPU");
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for (n=0; n<1000;n=n+1)
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check();
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if (fail==0) $display("passed");
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$display("------------------------");
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$finish;
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end
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endmodule
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