25 lines
534 B
Coq
25 lines
534 B
Coq
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/**
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* SPI controller for W25Q16BV
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*
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* When load=1 transmission of byte in[7:0] is initiated. The byte is send to
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* MOSI (master out slave in) bitwise together with 8 clock signals on SCK.
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* At the same time the SPI recieves a byte at MISO (master in slave out).
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* Sampling of MISO is done at rising edge of SCK and shiftingis done at
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*/
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`default_nettype none
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module SPI(
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input clk,
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input load,
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input [15:0] in,
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output [15:0] out,
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output CSX,
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output SDO,
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input SDI,
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output SCK
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);
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// Put your code here:
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endmodule
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