73 lines
1.3 KiB
Coq
73 lines
1.3 KiB
Coq
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`timescale 10ns/1ns
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`default_nettype none
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module SRAM_D_tb();
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// IN,OUT
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reg clk = 0;
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reg load = 0;
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reg [15:0] in=0;
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wire [15:0] out;
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wire CSX;
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wire OEX;
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wire WEX;
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wire [15:0] DATA;
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// Part
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SRAM_D SRAM_D(
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.clk(clk),
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.load(load),
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.in(in),
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.out(out),
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.CSX(CSX),
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.OEX(OEX),
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.WEX(WEX),
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.DATA(DATA)
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);
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// Simulate
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always #2 clk=~clk;
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wire trigger;
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reg write;
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assign trigger = (n==4) || (n==8) || (n==12) || (n==16) || (n==20);
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always @(posedge clk) begin
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in <= $random;
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load <= trigger;
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write <= load;
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end
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reg [15:0] data;
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always @(posedge clk)
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if (load) data <= in;
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// Compare
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wire CSX_cmp = 0;
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wire OEX_cmp = write;
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wire WEX_cmp = ~write;
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wire [15:0] out_cmp = (~CSX_cmp&~OEX_cmp)?16'bzzzzzzzzzzzzzzzz:data;
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reg fail = 0;
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reg [31:0] n = 0;
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task check;
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#4
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if ((out!=out_cmp)||(CSX!=CSX_cmp)||(OEX!=OEX_cmp)||(WEX!=WEX_cmp))
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begin
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$display("FAIL: clk=%1b, load=%1b, in=%16b, out=%16b, CSX=%1b, OEX=%1b, SEX=%1b, DATA=%16b",clk,load,in,out,CSX,OEX,WEX,DATA);
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fail=1;
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end
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endtask
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initial begin
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$dumpfile("SRAM_D_tb.vcd");
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$dumpvars(0, SRAM_D_tb);
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$display("------------------------");
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$display("Testbench: SRAM_D");
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for (n=0; n<24;n=n+1)
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check();
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if (fail==0) $display("passed");
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$display("------------------------");
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$finish;
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end
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endmodule
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