2023-01-11 10:13:09 +00:00
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/**
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* 16-bit register:
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* If load[t] == 1 then out[t+1] = in[t]
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* else out does not change
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*/
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`default_nettype none
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module Register(
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2024-10-17 18:36:58 +00:00
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input clk,
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input [15:0] in,
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input load,
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output [15:0] out
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2023-01-11 10:13:09 +00:00
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);
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2024-10-17 18:36:58 +00:00
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// Put your code here:
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Bit BITA(clk, in[0], load, out[0]);
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Bit BITB(clk, in[1], load, out[1]);
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Bit BITC(clk, in[2], load, out[2]);
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Bit BITD(clk, in[3], load, out[3]);
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Bit BITE(clk, in[4], load, out[4]);
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Bit BITF(clk, in[5], load, out[5]);
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Bit BITG(clk, in[6], load, out[6]);
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Bit BITH(clk, in[7], load, out[7]);
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Bit BITI(clk, in[8], load, out[8]);
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Bit BITJ(clk, in[9], load, out[9]);
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Bit BITK(clk, in[10], load, out[10]);
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Bit BITL(clk, in[11], load, out[11]);
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Bit BITM(clk, in[12], load, out[12]);
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Bit BITN(clk, in[13], load, out[13]);
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Bit BITO(clk, in[14], load, out[14]);
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Bit BITP(clk, in[15], load, out[15]);
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2023-01-11 10:13:09 +00:00
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endmodule
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