nand2/03_Sequential_Logic/RAM512.v

/**
* RAM512 implements 512 Bytes of RAM addressed from 0 - 511
* out = M[address]
* if (load =i= 1) M[address][t+1] = in[t]
*/

`default_nettype none
module RAM512(
    input clk,
    input [8:0] address,
    input [15:0] in,
    input load,
    output [15:0] out
);

    // Put your code here:
    wire load0;
    wire load1;
    wire [15:0] ram0;
    wire [15:0] ram1;
    DMux DMUX(load, address[8], load0, load1);
    RAM256 RAM0(clk, address[7:0], in, load0, ram0);
    RAM256 RAM1(clk, address[7:0], in, load1, ram1);
    Mux16 MUX(ram0, ram1, address[8], out);

endmodule