26 lines
1.0 KiB
Markdown
26 lines
1.0 KiB
Markdown
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# 02 Arithmetic Logic
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Proceed and implement the chips `HalfAdder`, `FullAdder`, `Add16`, `Inc16` and `ALU`.
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Keep in mind the following remarks:
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* in order to use the chips implemented in project `01_Boolean_Logic`, they must be listed in the file `Include.v`, which can be found in every subfolder.
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* you dan use a `Buffer` to split the signal wires. e.g. `ng` signal of ALU can be derived from out[15].
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* clear cache every time you edit and change your implementation in the verilog file `<chipname>.v`.
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* test your chip implementation with:
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```
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$ cd <XX_chipname>
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$ apio clean
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$ apio sim
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```
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* the chip `HalfAdder` can be uploaded to iCE40HX1K-EVB and tested using BUT1/2 and LED1/2. Keep in mind, that due to pull up resistors at the buttons, the signals appear inverted:
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| pin | function |
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| ------ | --------------------------------------------------- |
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| LED1/2 | =0 led is off, =1 led is on |
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| BUT1/2 | =0 button is pressed down, =1 button is released up |
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